[www-scripts] Clang Attribute Doc Update: SUCCESS
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Thu Feb 23 03:00:57 PST 2017
UPDATING /opt/clang_commandline_docs//src/llvm LLVM SOURCES
Updating '.':
U test/Transforms/NewGVN/edge.ll
U test/Transforms/NewGVN/condprop.ll
U test/Transforms/InstCombine/amdgcn-intrinsics.ll
U test/Transforms/SLPVectorizer/X86/horizontal-list.ll
U test/Transforms/Util/PredicateInfo/condprop.ll
U test/Transforms/Util/PredicateInfo/edge.ll
A test/Transforms/SampleProfile/Inputs/indirect-call.afdo
A test/Transforms/SampleProfile/indirect-call-gcc.ll
A test/Transforms/FunctionImport/unnamed-globals.ll
A test/Transforms/LoopVectorize/AArch64/pr31900.ll
U test/Transforms/LoopVectorize/float-induction.ll
U test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll
U test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores-private.ll
A test/Transforms/LoopStrengthReduce/X86/canonical.ll
A test/MC/WebAssembly
A test/MC/WebAssembly/file-headers.ll
A test/MC/WebAssembly/lit.local.cfg
U test/MC/AMDGPU/gfx7_asm_all.s
U test/MC/AMDGPU/gfx8_asm_all.s
U test/MC/AMDGPU/vop2.s
U test/MC/AMDGPU/regression/bug28168.s
U test/CodeGen/AMDGPU/trap.ll
U test/CodeGen/AMDGPU/amdgpu.private-memory.ll
U test/CodeGen/AMDGPU/wqm.ll
U test/CodeGen/AMDGPU/insert_vector_elt.ll
U test/CodeGen/AMDGPU/private-element-size.ll
A test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.ll
U test/CodeGen/AMDGPU/local-stack-slot-bug.ll
U test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
A test/CodeGen/AMDGPU/bfe-patterns.ll
U test/CodeGen/AMDGPU/extload-private.ll
U test/CodeGen/AMDGPU/llvm.amdgcn.exp.compr.ll
U test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
U test/CodeGen/AMDGPU/cgp-addressing-modes.ll
U test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
U test/CodeGen/AMDGPU/kernarg-stack-alignment.ll
U test/CodeGen/AMDGPU/spill-wide-sgpr.ll
U test/CodeGen/AMDGPU/spill-m0.ll
U test/CodeGen/AMDGPU/scratch-buffer.ll
U test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.ll
U test/CodeGen/AMDGPU/array-ptr-calc-i32.ll
A test/CodeGen/AMDGPU/clamp-modifier.ll
U test/CodeGen/AMDGPU/si-sgpr-spill.ll
A test/CodeGen/AMDGPU/clamp-omod-special-case.mir
A test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
U test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll
U test/CodeGen/AMDGPU/clamp.ll
U test/CodeGen/AMDGPU/captured-frame-index.ll
U test/CodeGen/AMDGPU/commute-compares.ll
A test/CodeGen/WebAssembly/f16.ll
U test/CodeGen/PowerPC/ppc64le-aggregates.ll
U test/CodeGen/ARM/fp16-promote.ll
U test/CodeGen/ARM/load-combine.ll
U test/CodeGen/ARM/load-combine-big-endian.ll
U test/CodeGen/X86/implicit-use-spill.mir
U test/CodeGen/X86/load-combine.ll
U test/CodeGen/X86/vector-half-conversions.ll
A test/CodeGen/X86/GlobalISel/binop-isel.ll
A test/CodeGen/X86/GlobalISel/legalize-sub.mir
A test/CodeGen/X86/GlobalISel/x86_64-instructionselect.mir
U test/CodeGen/MIR/Generic/runPass.mir
U test/CodeGen/MIR/Generic/llvmIRMissing.mir
U test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir
U test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
U test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
U test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
U test/CodeGen/AVR/pseudo/CPCWRdRr.mir
U test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
U test/CodeGen/AVR/pseudo/SBCWRdRr.mir
U test/CodeGen/AVR/pseudo/FRMIDX.mir
U test/CodeGen/AVR/pseudo/LDDWRdYQ.mir
U test/CodeGen/AVR/pseudo/COMWRd.mir
U test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
U test/CodeGen/AVR/pseudo/STWPtrPdRr.mir
U test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
U test/CodeGen/AVR/pseudo/STWPtrPiRr.mir
U test/CodeGen/AVR/pseudo/ORWRdRr.mir
U test/CodeGen/AVR/pseudo/LDWRdPtr.mir
U test/CodeGen/AVR/pseudo/ANDIWRdK.mir
U test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir
U test/CodeGen/AVR/pseudo/STWPtrRr.mir
U test/CodeGen/AVR/pseudo/LSLWRd.mir
U test/CodeGen/AVR/pseudo/ADDWRdRr.mir
U test/CodeGen/AVR/pseudo/PUSHWRr.mir
U test/CodeGen/AVR/pseudo/POPWRd.mir
U test/CodeGen/AVR/pseudo/LSRWRd.mir
U test/CodeGen/AVR/pseudo/STSWKRr.mir
U test/CodeGen/AVR/pseudo/ANDWRdRr.mir
U test/CodeGen/AVR/pseudo/SUBIWRdK.mir
U test/CodeGen/AVR/pseudo/ZEXT.mir
U test/CodeGen/AVR/pseudo/LDIWRdK.mir
U test/CodeGen/AVR/pseudo/ASRWRd.mir
U test/CodeGen/AVR/pseudo/OUTWARr.mir
U test/CodeGen/AVR/pseudo/EORWRdRr.mir
U test/CodeGen/AVR/pseudo/SBCIWRdK.mir
U test/CodeGen/AVR/pseudo/ADCWRdRr.mir
U test/CodeGen/AVR/pseudo/LDSWRdK.mir
U test/CodeGen/AVR/pseudo/SUBWRdRr.mir
U test/CodeGen/AVR/pseudo/ORIWRdK.mir
U test/CodeGen/AVR/pseudo/SEXT.mir
U test/CodeGen/AVR/pseudo/CPWRdRr.mir
U test/CodeGen/AVR/pseudo/INWRdA.mir
U test/CodeGen/AVR/inline-asm/inline-asm.ll
U test/CodeGen/AVR/inline-asm/inline-asm2.ll
U test/CodeGen/AVR/inline-asm/multibyte.ll
U test/CodeGen/AArch64/load-combine-big-endian.ll
U test/CodeGen/AArch64/ldst-opt.mir
U test/CodeGen/AArch64/arm64-regress-opt-cmp.mir
A test/CodeGen/AArch64/machine-copy-remove.mir
U test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
U test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
U test/CodeGen/AArch64/GlobalISel/legalize-or.mir
U test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
U test/CodeGen/AArch64/GlobalISel/legalize-div.mir
U test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
U test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
U test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
U test/CodeGen/AArch64/GlobalISel/legalize-add.mir
U test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
U test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
U test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
U test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
U test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
U test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
U test/CodeGen/AArch64/GlobalISel/legalize-and.mir
U test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
U test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
U test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
U test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
U test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
U test/CodeGen/AArch64/GlobalISel/legalize-gep.mir
U test/CodeGen/AArch64/load-combine.ll
U test/CodeGen/AArch64/movimm-wzr.mir
A test/CodeGen/Hexagon/readcyclecounter.ll
A test/CodeGen/Hexagon/intrinsics/byte-store-double.ll
A test/CodeGen/Hexagon/intrinsics/byte-store.ll
U test/CodeGen/Hexagon/expand-condsets-rm-reg.mir
U test/tools/llvm-objdump/wasm.txt
U test/tools/llvm-objdump/Inputs/test.wasm
U test/tools/llvm-readobj/file-headers.test
U test/tools/llvm-readobj/Inputs/trivial.obj.wasm
U cmake/config-ix.cmake
U include/llvm/IR/IntrinsicsAMDGPU.td
U include/llvm/IR/IntrinsicsHexagon.td
U include/llvm/IR/Dominators.h
U include/llvm/Target/TargetOptions.h
U include/llvm/Support/Wasm.h
U include/llvm/Transforms/Utils/PredicateInfo.h
U include/llvm/Transforms/Utils/MemorySSA.h
U include/llvm/Transforms/Utils/MemorySSAUpdater.h
U include/llvm/CodeGen/ScheduleDAGMutation.h
U include/llvm/CodeGen/ScheduleHazardRecognizer.h
U include/llvm/CodeGen/ScheduleDFS.h
U include/llvm/CodeGen/ScheduleDAG.h
U include/llvm/CodeGen/ScoreboardHazardRecognizer.h
U include/llvm/CodeGen/StackMaps.h
U include/llvm/CodeGen/MachineScheduler.h
U include/llvm/CodeGen/StackProtector.h
U docs/LangRef.rst
U unittests/Transforms/Utils/MemorySSA.cpp
U unittests/MI/LiveIntervalTest.cpp
U unittests/Support/Path.cpp
U lib/CodeGen/StackMaps.cpp
U lib/CodeGen/StackProtector.cpp
U lib/CodeGen/GlobalISel/InstructionSelector.cpp
U lib/CodeGen/ScheduleDAG.cpp
U lib/CodeGen/SelectionDAG/DAGCombiner.cpp
U lib/CodeGen/MachineScheduler.cpp
U lib/CodeGen/ScoreboardHazardRecognizer.cpp
U lib/Object/ArchiveWriter.cpp
U lib/IR/AutoUpgrade.cpp
U lib/Support/Unix/Path.inc
U lib/Analysis/ModuleSummaryAnalysis.cpp
U lib/Fuzzer/test/trace-malloc.test
U lib/Fuzzer/test/fuzzer-traces-hooks.test
A lib/Fuzzer/test/trace-malloc-2.test
U lib/Fuzzer/test/lit.cfg
U lib/Target/AMDGPU/EvergreenInstructions.td
U lib/Target/AMDGPU/SIInstrFormats.td
U lib/Target/AMDGPU/SIInstrInfo.td
U lib/Target/AMDGPU/SIFoldOperands.cpp
U lib/Target/AMDGPU/SIFrameLowering.cpp
U lib/Target/AMDGPU/AMDGPUSubtarget.h
U lib/Target/AMDGPU/AMDGPUInstructions.td
U lib/Target/AMDGPU/VOPInstructions.td
U lib/Target/AMDGPU/SIInstructions.td
U lib/Target/AMDGPU/SIISelLowering.cpp
U lib/Target/AMDGPU/SIInstrInfo.h
U lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
U lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
U lib/Target/AMDGPU/SIDefines.h
U lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
A lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.h
A lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp
U lib/Target/WebAssembly/CMakeLists.txt
U lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
U lib/Target/NVPTX/NVPTXISelLowering.cpp
A lib/Target/X86/X86InstructionSelector.cpp
U lib/Target/X86/X86LegalizerInfo.cpp
U lib/Target/X86/X86InstrAVX512.td
U lib/Target/X86/X86RegisterBankInfo.cpp
U lib/Target/X86/X86ISelLowering.cpp
A lib/Target/X86/X86InstructionSelector.h
U lib/Target/X86/X86InstrInfo.cpp
U lib/Target/X86/X86TargetMachine.cpp
U lib/Target/X86/X86InstrSSE.td
U lib/Target/X86/X86ShuffleDecodeConstantPool.cpp
U lib/Target/X86/CMakeLists.txt
U lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
U lib/Target/Hexagon/RDFLiveness.cpp
U lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
U lib/Target/Hexagon/HexagonRegisterInfo.td
U lib/Target/Hexagon/RDFRegisters.h
U lib/Target/Hexagon/HexagonPatterns.td
U lib/Target/Hexagon/HexagonISelLowering.cpp
U lib/Target/Hexagon/HexagonIntrinsics.td
U lib/Target/Hexagon/HexagonISelLowering.h
U lib/Target/Hexagon/RDFGraph.cpp
U lib/Target/Hexagon/RDFRegisters.cpp
U lib/Target/Hexagon/HexagonRegisterInfo.cpp
U lib/ProfileData/SampleProfReader.cpp
U lib/Transforms/Utils/MemorySSAUpdater.cpp
U lib/Transforms/Utils/PredicateInfo.cpp
U lib/Transforms/Utils/MemorySSA.cpp
U lib/Transforms/Scalar/GVNHoist.cpp
U lib/Transforms/Scalar/EarlyCSE.cpp
U lib/Transforms/Scalar/LoopStrengthReduce.cpp
U lib/Transforms/Scalar/NewGVN.cpp
U lib/Transforms/InstCombine/InstCombineCalls.cpp
U lib/Transforms/InstCombine/InstCombineAddSub.cpp
U lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
U lib/Transforms/Vectorize/SLPVectorizer.cpp
U lib/Transforms/Vectorize/LoopVectorize.cpp
U lib/MC/WasmObjectWriter.cpp
Updated to revision 295954.
UPDATING /opt/clang_commandline_docs//src/llvm/llvm/tools/clang CLANG SOURCES
Updating '.':
U tools/c-index-test/c-index-test.c
U lib/Serialization/ASTReader.cpp
U lib/Basic/Targets.cpp
U lib/Sema/SemaLookup.cpp
U lib/Sema/SemaExpr.cpp
U lib/Sema/Sema.cpp
U lib/Sema/SemaTemplateInstantiate.cpp
U lib/Sema/SemaDeclCXX.cpp
U lib/Sema/SemaDecl.cpp
U lib/Sema/SemaTemplateInstantiateDecl.cpp
U lib/Sema/SemaTemplateDeduction.cpp
U lib/Sema/SemaTemplate.cpp
U lib/Sema/SemaType.cpp
U lib/AST/StmtProfile.cpp
U lib/AST/ODRHash.cpp
U lib/AST/ASTContext.cpp
U lib/AST/DeclObjC.cpp
U lib/AST/ExprConstant.cpp
U lib/CodeGen/CGClass.cpp
U lib/CodeGen/CGCXXABI.h
U lib/CodeGen/MicrosoftCXXABI.cpp
U lib/CodeGen/ItaniumCXXABI.cpp
U lib/CodeGen/CGException.cpp
U lib/CodeGen/CGCall.cpp
U lib/CodeGen/CodeGenFunction.h
U lib/CodeGen/CGBuiltin.cpp
U lib/CodeGen/CGExpr.cpp
U lib/CodeGen/CGExprCXX.cpp
U test/SemaTemplate/temp_arg_template_cxx1z.cpp
A test/CodeGenObjCXX/arc-attrs-abi.mm
U test/CXX/drs/dr4xx.cpp
U test/CodeGen/pass-object-size.c
A test/CodeGenOpenCL/builtins-amdgcn-gfx9.cl
U test/CodeGenOpenCL/amdgpu-abi-struct-coerce.cl
U test/Modules/odr_hash.cpp
U test/Modules/Inputs/category_right_sub.h
U test/Modules/objc-categories.m
U test/SemaCXX/cxx1y-generic-lambdas.cpp
U test/SemaCXX/constant-expression-cxx11.cpp
U test/SemaCXX/make_integer_seq.cpp
U test/SemaCXX/libstdcxx_pair_swap_hack.cpp
A test/SemaOpenCL/builtins-amdgcn-error-gfx9.cl
U test/SemaOpenCL/builtins-amdgcn-error-f16.cl
U test/CodeGenCXX/exceptions-seh.cpp
U include/clang/Basic/BuiltinsAMDGPU.def
U include/clang/Basic/DiagnosticSerializationKinds.td
U include/clang/Sema/Sema.h
U include/clang/AST/Stmt.h
Updated to revision 295954.
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