[Openmp-commits] [PATCH] D94745: [OpenMP][WIP] Build the deviceRTLs with OpenMP instead of target dependent language - NOT FOR REVIEW

[Shilei Tian via Phabricator via Openmp-commits]

tianshilei1992 added a comment.

>From the IR generated, seems like OpenMP cannot handle these operations except `atomicAdd`.

  ; Function Attrs: noinline nounwind optnone mustprogress
  define linkonce_odr hidden i32 @_Z17__kmpc_atomic_addIiET_PS0_S0_(i32* %Address, i32 %Val) #3 comdat {
  entry:
    %Address.addr = alloca i32*, align 8
    %Val.addr = alloca i32, align 4
    %Old = alloca i32, align 4
    store i32* %Address, i32** %Address.addr, align 8
    store i32 %Val, i32* %Val.addr, align 4
    %0 = load i32*, i32** %Address.addr, align 8
    %1 = load i32, i32* %Val.addr, align 4
    %2 = atomicrmw add i32* %0, i32 %1 monotonic
    store i32 %2, i32* %Old, align 4
    %3 = load i32, i32* %Old, align 4
    ret i32 %3
  }
  
  ; Function Attrs: noinline nounwind optnone mustprogress
  define linkonce_odr hidden i32 @_Z17__kmpc_atomic_incIiET_PS0_S0_(i32* %Address, i32 %Val) #3 comdat {
  entry:
    %Address.addr = alloca i32*, align 8
    %Val.addr = alloca i32, align 4
    %Old = alloca i32, align 4
    store i32* %Address, i32** %Address.addr, align 8
    store i32 %Val, i32* %Val.addr, align 4
    %0 = load i32*, i32** %Address.addr, align 8
    %1 = load i32, i32* %Old, align 4
    %2 = load i32, i32* %Val.addr, align 4
    %cmp = icmp sge i32 %1, %2
    br i1 %cmp, label %cond.true, label %cond.false
  
  cond.true:                                        ; preds = %entry
    br label %cond.end
  
  cond.false:                                       ; preds = %entry
    %3 = load i32, i32* %Old, align 4
    %add = add nsw i32 %3, 1
    br label %cond.end
  
  cond.end:                                         ; preds = %cond.false, %cond.true
    %cond = phi i32 [ 0, %cond.true ], [ %add, %cond.false ]
    %4 = atomicrmw xchg i32* %0, i32 %cond monotonic
    store i32 %4, i32* %Old, align 4
    %5 = load i32, i32* %Old, align 4
    ret i32 %5
  }
  
  ; Function Attrs: noinline nounwind optnone mustprogress
  define linkonce_odr hidden i32 @_Z17__kmpc_atomic_maxIiET_PS0_S0_(i32* %Address, i32 %Val) #3 comdat {
  entry:
    %Address.addr = alloca i32*, align 8
    %Val.addr = alloca i32, align 4
    %Old = alloca i32, align 4
    store i32* %Address, i32** %Address.addr, align 8
    store i32 %Val, i32* %Val.addr, align 4
    %0 = load i32*, i32** %Address.addr, align 8
    %1 = load i32, i32* %Old, align 4
    %2 = load i32, i32* %Val.addr, align 4
    %cmp = icmp sgt i32 %1, %2
    br i1 %cmp, label %cond.true, label %cond.false
  
  cond.true:                                        ; preds = %entry
    %3 = load i32, i32* %Old, align 4
    br label %cond.end
  
  cond.false:                                       ; preds = %entry
    %4 = load i32, i32* %Val.addr, align 4
    br label %cond.end
  
  cond.end:                                         ; preds = %cond.false, %cond.true
    %cond = phi i32 [ %3, %cond.true ], [ %4, %cond.false ]
    %5 = atomicrmw xchg i32* %0, i32 %cond monotonic
    store i32 %5, i32* %Old, align 4
    %6 = load i32, i32* %Old, align 4
    ret i32 %6
  }
  
  ; Function Attrs: noinline nounwind optnone mustprogress
  define linkonce_odr hidden i32 @_Z22__kmpc_atomic_exchangeIiET_PS0_S0_(i32* %Address, i32 %Val) #3 comdat {
  entry:
    %Address.addr = alloca i32*, align 8
    %Val.addr = alloca i32, align 4
    %Old = alloca i32, align 4
    store i32* %Address, i32** %Address.addr, align 8
    store i32 %Val, i32* %Val.addr, align 4
    %0 = load i32*, i32** %Address.addr, align 8
    %1 = load i32, i32* %Val.addr, align 4
    %2 = atomicrmw xchg i32* %0, i32 %1 monotonic
    store i32 %2, i32* %Old, align 4
    %3 = load i32, i32* %Old, align 4
    ret i32 %3
  }
  
  ; Function Attrs: noinline nounwind optnone mustprogress
  define linkonce_odr hidden i32 @_Z17__kmpc_atomic_casIiET_PS0_S0_S0_(i32* %Address, i32 %Compare, i32 %Val) #3 comdat {
  entry:
    %Address.addr = alloca i32*, align 8
    %Compare.addr = alloca i32, align 4
    %Val.addr = alloca i32, align 4
    %Old = alloca i32, align 4
    store i32* %Address, i32** %Address.addr, align 8
    store i32 %Compare, i32* %Compare.addr, align 4
    store i32 %Val, i32* %Val.addr, align 4
    %0 = load i32*, i32** %Address.addr, align 8
    %1 = load i32, i32* %Old, align 4
    %2 = load i32, i32* %Compare.addr, align 4
    %cmp = icmp eq i32 %1, %2
    br i1 %cmp, label %cond.true, label %cond.false
  
  cond.true:                                        ; preds = %entry
    %3 = load i32, i32* %Val.addr, align 4
    br label %cond.end
  
  cond.false:                                       ; preds = %entry
    %4 = load i32, i32* %Old, align 4
    br label %cond.end
  
  cond.end:                                         ; preds = %cond.false, %cond.true
    %cond = phi i32 [ %3, %cond.true ], [ %4, %cond.false ]
    %5 = atomicrmw xchg i32* %0, i32 %cond monotonic
    store i32 %5, i32* %Old, align 4
    %6 = load i32, i32* %Old, align 4
    ret i32 %6
  }

Reading from `Address` to `Old` and all following operations are NOT one atomic transaction.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94745/new/

https://reviews.llvm.org/D94745