[Mlir-commits] [mlir] 6c75b01 - [mlir][LLVM] Add smulh and umulh intrinsics. (#226776)

[llvmlistbot at llvm.org]

Author: Letu Ren
Date: 2026-09-28T08:53:48+08:00
New Revision: 6c75b015778cdb22d688d6c6f6e40ccb6d9eb352

URL: https://github.com/llvm/llvm-project/commit/6c75b015778cdb22d688d6c6f6e40ccb6d9eb352
DIFF: https://github.com/llvm/llvm-project/commit/6c75b015778cdb22d688d6c6f6e40ccb6d9eb352.diff

LOG: [mlir][LLVM] Add smulh and umulh intrinsics. (#226776)

Assisted-by: grok-4.7
Signed-off-by: Letu Ren <fantasquex at gmail.com>

Added: 
    

Modified: 
    mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
    mlir/test/Dialect/LLVMIR/roundtrip.mlir
    mlir/test/Target/LLVMIR/Import/intrinsic.ll
    mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir

Removed: 
    


################################################################################
diff  --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
index 15c2ae2076a90..b226852ee4c6f 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
@@ -197,6 +197,8 @@ def LLVM_FshrOp : LLVM_TernarySameArgsIntrOpI<"fshr">;
 def LLVM_ClmulOp : LLVM_BinarySameArgsIntrOpI<"clmul">;
 def LLVM_PdepOp : LLVM_BinarySameArgsIntrOpI<"pdep">;
 def LLVM_PextOp : LLVM_BinarySameArgsIntrOpI<"pext">;
+def LLVM_SMulHOp : LLVM_BinarySameArgsIntrOpI<"smulh">;
+def LLVM_UMulHOp : LLVM_BinarySameArgsIntrOpI<"umulh">;
 def LLVM_MaxNumOp : LLVM_BinarySameArgsIntrOpF<"maxnum">;
 def LLVM_MinNumOp : LLVM_BinarySameArgsIntrOpF<"minnum">;
 def LLVM_MaximumOp : LLVM_BinarySameArgsIntrOpF<"maximum">;

diff  --git a/mlir/test/Dialect/LLVMIR/roundtrip.mlir b/mlir/test/Dialect/LLVMIR/roundtrip.mlir
index 2659a0c482f18..6ef571efe5c51 100644
--- a/mlir/test/Dialect/LLVMIR/roundtrip.mlir
+++ b/mlir/test/Dialect/LLVMIR/roundtrip.mlir
@@ -281,6 +281,12 @@ func.func @ops(%arg0: i32, %arg1: f32,
 // CHECK: llvm.intr.clmul(%{{.*}}, %{{.*}}) : (i32, i32) -> i32
   %clmul = llvm.intr.clmul(%arg0, %arg0) : (i32, i32) -> i32
 
+// CHECK: llvm.intr.smulh(%{{.*}}, %{{.*}}) : (i32, i32) -> i32
+  %smulh = llvm.intr.smulh(%arg0, %arg0) : (i32, i32) -> i32
+
+// CHECK: llvm.intr.umulh(%{{.*}}, %{{.*}}) : (i32, i32) -> i32
+  %umulh = llvm.intr.umulh(%arg0, %arg0) : (i32, i32) -> i32
+
 // CHECK: llvm.intr.ctpop(%{{.*}}) : (i32) -> i32
   %33 = llvm.intr.ctpop(%arg0) : (i32) -> i32
 

diff  --git a/mlir/test/Target/LLVMIR/Import/intrinsic.ll b/mlir/test/Target/LLVMIR/Import/intrinsic.ll
index a2f3df554f4a8..f5d4cc9a113c5 100644
--- a/mlir/test/Target/LLVMIR/Import/intrinsic.ll
+++ b/mlir/test/Target/LLVMIR/Import/intrinsic.ll
@@ -407,6 +407,24 @@ define void @pext_test(i32 %0, i32 %1, <8 x i32> %2, <8 x i32> %3) {
   ret void
 }
 
+; CHECK-LABEL:  llvm.func @smulh_test
+define void @smulh_test(i32 %0, i32 %1, <8 x i32> %2, <8 x i32> %3) {
+  ; CHECK:   llvm.intr.smulh(%{{.*}}, %{{.*}}) : (i32, i32) -> i32
+  %5 = call i32 @llvm.smulh.i32(i32 %0, i32 %1)
+  ; CHECK:   llvm.intr.smulh(%{{.*}}, %{{.*}}) : (vector<8xi32>, vector<8xi32>) -> vector<8xi32>
+  %6 = call <8 x i32> @llvm.smulh.v8i32(<8 x i32> %2, <8 x i32> %3)
+  ret void
+}
+
+; CHECK-LABEL:  llvm.func @umulh_test
+define void @umulh_test(i32 %0, i32 %1, <8 x i32> %2, <8 x i32> %3) {
+  ; CHECK:   llvm.intr.umulh(%{{.*}}, %{{.*}}) : (i32, i32) -> i32
+  %5 = call i32 @llvm.umulh.i32(i32 %0, i32 %1)
+  ; CHECK:   llvm.intr.umulh(%{{.*}}, %{{.*}}) : (vector<8xi32>, vector<8xi32>) -> vector<8xi32>
+  %6 = call <8 x i32> @llvm.umulh.v8i32(<8 x i32> %2, <8 x i32> %3)
+  ret void
+}
+
 ; CHECK-LABEL:  llvm.func @maximum_test
 define void @maximum_test(float %0, float %1, <8 x float> %2, <8 x float> %3) {
   ; CHECK:   llvm.intr.maximum(%{{.*}}, %{{.*}}) : (f32, f32) -> f32
@@ -1856,6 +1874,10 @@ declare i32 @llvm.pdep.i32(i32, i32)
 declare <8 x i32> @llvm.pdep.v8i32(<8 x i32>, <8 x i32>)
 declare i32 @llvm.pext.i32(i32, i32)
 declare <8 x i32> @llvm.pext.v8i32(<8 x i32>, <8 x i32>)
+declare i32 @llvm.smulh.i32(i32, i32)
+declare <8 x i32> @llvm.smulh.v8i32(<8 x i32>, <8 x i32>)
+declare i32 @llvm.umulh.i32(i32, i32)
+declare <8 x i32> @llvm.umulh.v8i32(<8 x i32>, <8 x i32>)
 declare float @llvm.maximum.f32(float, float)
 declare <8 x float> @llvm.maximum.v8f32(<8 x float>, <8 x float>)
 declare float @llvm.minimum.f32(float, float)

diff  --git a/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir b/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
index 7752226de882d..865aa62003194 100644
--- a/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
+++ b/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir
@@ -432,6 +432,24 @@ llvm.func @pext_test(%arg0: i32, %arg1: i32, %arg2: vector<8xi32>, %arg3: vector
   llvm.return
 }
 
+// CHECK-LABEL: @smulh_test
+llvm.func @smulh_test(%arg0: i32, %arg1: i32, %arg2: vector<8xi32>, %arg3: vector<8xi32>) {
+  // CHECK: call i32 @llvm.smulh.i32
+  "llvm.intr.smulh"(%arg0, %arg1) : (i32, i32) -> i32
+  // CHECK: call <8 x i32> @llvm.smulh.v8i32
+  "llvm.intr.smulh"(%arg2, %arg3) : (vector<8xi32>, vector<8xi32>) -> vector<8xi32>
+  llvm.return
+}
+
+// CHECK-LABEL: @umulh_test
+llvm.func @umulh_test(%arg0: i32, %arg1: i32, %arg2: vector<8xi32>, %arg3: vector<8xi32>) {
+  // CHECK: call i32 @llvm.umulh.i32
+  "llvm.intr.umulh"(%arg0, %arg1) : (i32, i32) -> i32
+  // CHECK: call <8 x i32> @llvm.umulh.v8i32
+  "llvm.intr.umulh"(%arg2, %arg3) : (vector<8xi32>, vector<8xi32>) -> vector<8xi32>
+  llvm.return
+}
+
 // CHECK-LABEL: @maximum_test
 llvm.func @maximum_test(%arg0: f32, %arg1: f32, %arg2: vector<8xf32>, %arg3: vector<8xf32>) {
   // CHECK: call float @llvm.maximum.f32