[Mlir-commits] [mlir] [mlir][x86] Add extra patterns for AMX nano-kernel lowering (acc with zero constant) (PR #222513)

[Julian Oppermann]

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@@ -1418,22 +1446,20 @@ struct VectorContractToAMXDotProduct
     Value srcBuffAcc;
     SmallVector<Value> indicesAcc;
 
-    llvm::TypeSwitch<Operation *>(accReadOp).Case<TransferReadOp, LoadOp>(
-        [&](auto readOp) {
-          srcBuffAcc = readOp.getOperand(0);
+    llvm::TypeSwitch<Operation *>(accWrite)
+        .Case<vector::TransferWriteOp, vector::StoreOp>([&](auto writeOp) {
+          srcBuffAcc = writeOp->getOperand(1);
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jopperm wrote:

ACK, sorry for sending you onto the dominance/insertion-point detour.

I now think the underlying problem is taking the memref from the write op. (We don't enforce read and write to use the same memref, and it would seem unnecessary to do so.)

My suggestion is to keep using the read's memref for `srcBuffAcc`. `srcBuffAcc` is used for loading the initial value _if the acc is not zero-initialised_, so it's guaranteed to be present. The other use is to define the `outputShapes` from the `srcBuffAcc`'s memref type. Can you query the shape from somewhere else? The current logic also breaks on dynamic shapes (`memref<?x?xf32>` results in `M=0` and `N=0` in your code).

https://github.com/llvm/llvm-project/pull/222513