[Mlir-commits] [mlir] [mlir][SPIR-V] Verify memory semantics for AtomicLoad/Store/Exchange/CompareExchange ops (PR #212990)

[Igor Wodiany]

================
@@ -109,6 +117,14 @@ func.func @atomic_compare_exchange_weak(%ptr: !spirv.ptr<i64, Workgroup>, %value
 
 // -----
 
+func.func @atomic_compare_exchange_weak(%ptr: !spirv.ptr<i32, Workgroup>, %value: i32, %comparator: i32) -> i32 {
+  // expected-error @+1 {{expected at most one of these four memory constraints to be set: `Acquire`, `Release`,`AcquireRelease` or `SequentiallyConsistent`}}
+  %0 = spirv.AtomicCompareExchangeWeak <Workgroup> <Acquire|Release> <None> %ptr, %value, %comparator: !spirv.ptr<i32, Workgroup>
----------------
IgWod wrote:

Same as above.

https://github.com/llvm/llvm-project/pull/212990