[Mlir-commits] [mlir] [mlir][linalg] Hoist masked vector transfer pairs (PR #221481)
Hugo Pompougnac
llvmlistbot at llvm.org
Thu Sep 17 05:13:57 PDT 2026
================
@@ -1443,3 +1443,229 @@ module attributes {transform.with_named_sequence} {
transform.yield
}
}
+
+// -----
+
+///----------------------------------------------------------------------------------------
+/// Tests for hoisting masked (`vector.mask`-wrapped) transfer pairs
+///----------------------------------------------------------------------------------------
+
+// A masked read/write pair sharing the same mask is hoisted as a whole: the
+// masked read/write move to the loop boundary while the value is carried
+// unmasked through an iter_arg.
+
+// CHECK-LABEL: func.func @hoist_masked_transfer_pair(
+// CHECK-SAME: %[[MEM:[a-zA-Z0-9]+]]: memref<?xf32>,
+// CHECK-SAME: %[[MASK:[a-zA-Z0-9]+]]: vector<4xi1>,
+// CHECK: %[[READ:.*]] = vector.mask %[[MASK]] {{.*}}transfer_read %[[MEM]]
+// CHECK: %[[FOR:.*]] = scf.for {{.*}} iter_args(%[[IARG:.*]] = %[[READ]]) -> (vector<4xf32>) {
+// CHECK-NEXT: %[[USE:.*]] = "test.val_use"(%[[IARG]])
+// CHECK-NEXT: scf.yield %[[USE]]
+// CHECK-NEXT: }
+// CHECK: vector.mask %[[MASK]] {{.*}}transfer_write %[[FOR]], %[[MEM]]
+func.func @hoist_masked_transfer_pair(%mem: memref<?xf32>, %mask: vector<4xi1>, %lb: index, %ub: index, %step: index) {
+ %c0 = arith.constant 0 : index
+ %pad = arith.constant 0.0 : f32
----------------
qaco wrote:
Ok
https://github.com/llvm/llvm-project/pull/221481
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