[Mlir-commits] [mlir] [mlir][gpu] Store the all-reduce result from the first lane only (PR #221532)

[Alessandro Potenza]

alepot55 wrote:

The interpreter is an executable semantics of the LLVM and NVVM dialects that I use to fuzz the gpu-to-nvvm pipeline: it runs the lowered module lane by lane and treats a store whose value differs across the lanes that reach it as undefined, and that is how the 3-warp case surfaced. No, I have not seen a wrong result on hardware: on an RTX PRO 6000 the value that lands is lane 0's, so as far as I can tell this is undefined by the lowering's own contract rather than a miscompile anyone hits, and I take your point that the pattern is not generic. I'm happy to reduce this to the comment fix you suggested and drop the predication; would that be the better patch?

https://github.com/llvm/llvm-project/pull/221532