[Mlir-commits] [mlir] [mlir][xegpu] Remove chunk_size attribute; infer from types (PR #205122)

[Jianhui Li]

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@@ -880,29 +881,37 @@ def XeGPU_StoreScatterOp : XeGPU_Op<"store", [MemoryEffects<[MemWrite]>, AnchorL
     %val = arith.constant dense<0.0> : vector<16xf32>
     %offsets = vector.step : vector<16xindex>
     %mask = vector.constant_mask [16]: vector<16xi1>
-    xegpu.store %val, %a[%offsets], %mask {l1_hint = #xegpu.cache_hint<cached>,
+    xegpu.store %val, %a[%offsets], %mask <{l1_hint = #xegpu.cache_hint<cached>,
                            l2_hint = #xegpu.cache_hint<cached>,
                            l3_hint = #xegpu.cache_hint<cached>,
-                           layout = #xegpu.layout<lane_layout = [16], lane_data = [1]>}
-      : vector<16xf32>, memref<1024xf32>, vector<16xi1>, vector<16xindex>
+                           layout = #xegpu.layout<lane_layout = [16], lane_data = [1]>}>
+      : vector<16xf32>, memref<1024xf32>, vector<16xindex>, vector<16xi1>
   ```
 
   Example 2 (Lane level):
-  Lane level IR only accepts the offsets variant. chunk_size can be inferred from value
-  type. In this example, chunk_size is 8.
+  Lane level IR only accepts the offsets variant. The mask, offsets, and value all
+  have the same shape; here each lane writes 8 elements.
   ```mlir
-    xegpu.store %0, %1[%2], %3 <{l1_hint = #xegpu.cache_hint<uncached>,
+    xegpu.store %val, %dest[%offsets], %mask <{l1_hint = #xegpu.cache_hint<uncached>,
                              l2_hint = #xegpu.cache_hint<write_back>,
                              l3_hint = #xegpu.cache_hint<write_through>}>
-          : vector<8xf32>, memref<256xf32>, vector<1xindex>, vector<1xi1>
+          : vector<8xf32>, memref<256xf32>, vector<8xindex>, vector<8xi1>
+  ```
+
+  Example 3 (Subgroup level, contiguous runs):
+  `contiguity` says each lane may take 4 neighbouring elements in one access.
----------------
Jianhui-Li wrote:

nit: `contiguity` indicates 4 neighboring elements in innermost dimension is contiguous.

https://github.com/llvm/llvm-project/pull/205122