[Mlir-commits] [mlir] [mlir][x86] Add extra patterns for AMX nano-kernel lowering (acc with zero constant) (PR #222513)

[Julian Oppermann]

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@@ -1418,22 +1446,20 @@ struct VectorContractToAMXDotProduct
     Value srcBuffAcc;
     SmallVector<Value> indicesAcc;
 
-    llvm::TypeSwitch<Operation *>(accReadOp).Case<TransferReadOp, LoadOp>(
-        [&](auto readOp) {
-          srcBuffAcc = readOp.getOperand(0);
+    llvm::TypeSwitch<Operation *>(accWrite)
+        .Case<vector::TransferWriteOp, vector::StoreOp>([&](auto writeOp) {
+          srcBuffAcc = writeOp->getOperand(1);
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jopperm wrote:

If we don't have a read of the accumulator memref before the contraction loop, it's possible that `writeOp`'s memref operand is defined right before `writeOp`, after the contraction loop. Testing with Triton CPU, I've observed that the shuffle-and-or-accumulate loop is inserted before `srcBuffAcc` was defined, so we need to be careful with the insertion point later (or alternatively move operations around).

https://github.com/llvm/llvm-project/pull/222513