[Mlir-commits] [mlir] [mlir][AMDGPU] Keep alignment when lowering masked loads and stores (PR #221308)

Hung-Kuan Tseng llvmlistbot at llvm.org
Fri Sep 11 08:01:08 PDT 2026

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Tim096 wrote:

Ping @krzysz00. Same shape as #221312, which you approved, on the AMDGPU side.

https://github.com/llvm/llvm-project/pull/221308

Previous message: [Mlir-commits] [mlir] [mlir][VectorToSCF] Decline transfer ops masked by vector.mask (PR #221307)
Next message: [Mlir-commits] [mlir] 325f255 - [flang][acc] Let getVariableName choose mangled or source names (#222815)
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