[Mlir-commits] [clang] [llvm] [mlir] [AMDGPU] Implement AsyncMark Stages (PR #220442)

[Sameer Sahasrabuddhe]

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@@ -4816,6 +4817,50 @@ bool SIInstrInfo::mayAccessLDSThroughFlat(const MachineInstr &MI,
   return false;
 }
 
+AMDGPU::AsyncStages SIInstrInfo::getAsyncStage(const MachineInstr &MI) {
+  if (!isLDSDMA(MI))
+    return AMDGPU::AsyncStages::NONE;
+  if (usesTENSOR_CNT(MI))
+    return AMDGPU::AsyncStages::TENSOR;
+  if (!usesASYNC_CNT(MI))
+    return AMDGPU::AsyncStages::BUFFER_GLOBAL_LOAD;
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ssahasra wrote:

Quoting copilot: AMDGPU::GLOBAL_LOAD_LDS_DWORD with its IsAsync operand set to 0. It passes isLDSDMA(), uses neither TENSOR_CNT nor ASYNC_CNT, and therefore incorrectly returns AsyncStages::BUFFER_GLOBAL_LOAD instead of NONE.

https://github.com/llvm/llvm-project/pull/220442