[Mlir-commits] [mlir] [mlir][ArmNeon/ArmSVE] Reorganise .td and test files (NFC) (PR #236797)
llvmlistbot at llvm.org
llvmlistbot at llvm.org
Thu Oct 29 07:52:29 PDT 2026
github-actions[bot] wrote:
<!--PREMERGE ADVISOR COMMENT: Windows-->
# :window: Windows x64 Test Results
* 4405 tests passed
* 467 tests skipped
* 2 tests failed
## Failed Tests
(click on a test name to see its output)
### MLIR
<details>
<summary>MLIR.Dialect/ArmSVE/invalid.mlir</summary>
```
Exit Code: 1
Command Output (stdout):
--
# RUN: at line 1
c:\_work\llvm-project\llvm-project\build\bin\mlir-opt.exe C:\_work\llvm-project\llvm-project\mlir\test\Dialect\ArmSVE\invalid.mlir -split-input-file -verify-diagnostics
# executed command: 'c:\_work\llvm-project\llvm-project\build\bin\mlir-opt.exe' 'C:\_work\llvm-project\llvm-project\mlir\test\Dialect\ArmSVE\invalid.mlir' -split-input-file -verify-diagnostics
# .---command stdout------------
# | // -----
# | // -----
# | // -----
# | // -----
# | // -----
# | // -----
# | // -----
# | // -----
# | // -----
# | // -----
# | // -----
# | // -----
# | // -----
# `-----------------------------
# .---command stderr------------
# | C:\_work\llvm-project\llvm-project\mlir\test\Dialect\ArmSVE\invalid.mlir:60:6: error: expected error "operand #0 must be scalable vector of 32-bit float values of length 4, but got 'vector<4xf32>'" was not produced
# | // expected-error at +1 {{operand #0 must be scalable vector of 32-bit float values of length 4, but got 'vector<4xf32>'}}
# | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# `-----------------------------
# error: command failed with exit status: 1
--
```
</details>
<details>
<summary>MLIR.Dialect/ArmSVE/legalize-for-llvm.mlir</summary>
```
Exit Code: 1
Command Output (stdout):
--
# RUN: at line 1
c:\_work\llvm-project\llvm-project\build\bin\mlir-opt.exe -convert-vector-to-llvm="enable-arm-sve" -convert-func-to-llvm -convert-arith-to-llvm -cse -reconcile-unrealized-casts -split-input-file C:\_work\llvm-project\llvm-project\mlir\test\Dialect\ArmSVE\legalize-for-llvm.mlir | c:\_work\llvm-project\llvm-project\build\bin\filecheck.exe C:\_work\llvm-project\llvm-project\mlir\test\Dialect\ArmSVE\legalize-for-llvm.mlir
# executed command: 'c:\_work\llvm-project\llvm-project\build\bin\mlir-opt.exe' -convert-vector-to-llvm=enable-arm-sve -convert-func-to-llvm -convert-arith-to-llvm -cse -reconcile-unrealized-casts -split-input-file 'C:\_work\llvm-project\llvm-project\mlir\test\Dialect\ArmSVE\legalize-for-llvm.mlir'
# note: command had no output on stdout or stderr
# executed command: 'c:\_work\llvm-project\llvm-project\build\bin\filecheck.exe' 'C:\_work\llvm-project\llvm-project\mlir\test\Dialect\ArmSVE\legalize-for-llvm.mlir'
# .---command stderr------------
# | C:\_work\llvm-project\llvm-project\mlir\test\Dialect\ArmSVE\legalize-for-llvm.mlir:284:17: error: CHECK-LABEL: expected string not found in input
# | // CHECK-LABEL: @arm_sve_unsupported_create_masks
# | ^
# | <stdin>:164:50: note: scanning from here
# | llvm.func @arm_sve_predicate_sized_create_masks(%arg0: i64) -> !llvm.struct<(vector<[2]xi1>, vector<[4]xi1>, vector<[8]xi1>, vector<[16]xi1>)> {
# | ^
# | <stdin>:221:12: note: possible intended match here
# | llvm.func @arm_sve_psel_mixed_predicate_types(%arg0: vector<[8]xi1>, %arg1: vector<[16]xi1>, %arg2: i64) -> vector<[8]xi1> {
# | ^
# |
# | Input file: <stdin>
# | Check file: C:\_work\llvm-project\llvm-project\mlir\test\Dialect\ArmSVE\legalize-for-llvm.mlir
# |
# | -dump-input=help explains the following input dump.
# |
# | Input was:
# | <<<<<<
# | .
# | .
# | .
# | 159: }
# | 160: }
# | 161:
# | 162: // -----
# | 163: module {
# | 164: llvm.func @arm_sve_predicate_sized_create_masks(%arg0: i64) -> !llvm.struct<(vector<[2]xi1>, vector<[4]xi1>, vector<[8]xi1>, vector<[16]xi1>)> {
# | label:284'0 { search range start (exclusive)
# | label:284'1 error: no match found in search range
# | 165: %0 = llvm.mlir.zero : i64
# | 166: %1 = "arm_sve.intr.whilelt"(%0, %arg0) : (i64, i64) -> vector<[2]xi1>
# | 167: %2 = "arm_sve.intr.whilelt"(%0, %arg0) : (i64, i64) -> vector<[4]xi1>
# | 168: %3 = "arm_sve.intr.whilelt"(%0, %arg0) : (i64, i64) -> vector<[8]xi1>
# | 169: %4 = "arm_sve.intr.whilelt"(%0, %arg0) : (i64, i64) -> vector<[16]xi1>
# | .
# | .
# | .
# | 216: }
# | 217: }
# | 218:
# | 219: // -----
# | 220: module {
# | 221: llvm.func @arm_sve_psel_mixed_predicate_types(%arg0: vector<[8]xi1>, %arg1: vector<[16]xi1>, %arg2: i64) -> vector<[8]xi1> {
# | label:284'2 ? possible intended match
# | 222: %0 = "arm_sve.intr.convert.to.svbool"(%arg0) : (vector<[8]xi1>) -> vector<[16]xi1>
# | 223: %1 = llvm.trunc %arg2 : i64 to i32
# | 224: %2 = "arm_sve.intr.psel"(%0, %arg1, %1) : (vector<[16]xi1>, vector<[16]xi1>, i32) -> vector<[16]xi1>
# | 225: %3 = "arm_sve.intr.convert.from.svbool"(%2) : (vector<[16]xi1>) -> vector<[8]xi1>
# | 226: llvm.return %3 : vector<[8]xi1>
# | .
# | .
# | .
# | 248: %15 = llvm.insertvalue %6, %14[6] : !llvm.struct<(vector<[16]xi8>, vector<[8]xi16>, vector<[8]xf16>, vector<[8]xbf16>, vector<[4]xi32>, vector<[4]xf32>, vector<[2]xi64>, vector<[2]xf64>)>
# | 249: %16 = llvm.insertvalue %7, %15[7] : !llvm.struct<(vector<[16]xi8>, vector<[8]xi16>, vector<[8]xf16>, vector<[8]xbf16>, vector<[4]xi32>, vector<[4]xf32>, vector<[2]xi64>, vector<[2]xf64>)>
# | 250: llvm.return %16 : !llvm.struct<(vector<[16]xi8>, vector<[8]xi16>, vector<[8]xf16>, vector<[8]xbf16>, vector<[4]xi32>, vector<[4]xf32>, vector<[2]xi64>, vector<[2]xf64>)>
# | 251: }
# | 252: }
# | 253:
# | label:284'3 } search range end (exclusive)
# | >>>>>>
# `-----------------------------
# error: command failed with exit status: 1
--
```
</details>
If these failures are unrelated to your changes (for example tests are broken or flaky at HEAD), please open an issue at https://github.com/llvm/llvm-project/issues and add the `infrastructure` label.
https://github.com/llvm/llvm-project/pull/236797
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