[Mlir-commits] [mlir] [mlir][spirv] Print storage class in spirv.INTEL.SubgroupBlockWrite (PR #235549)

Oskar Guzik llvmlistbot at llvm.org
Sun Oct 25 18:32:16 PDT 2026


https://github.com/osguzik created https://github.com/llvm/llvm-project/pull/235549

This prints the storage class which the parser requires, so the op round-trips. Updated the tests as well.

fixes #226050

>From f1f57329c9cc9a38ae5e581c6b252d654d58e8ca Mon Sep 17 00:00:00 2001
From: osguzik <os.guzik at proton.me>
Date: Mon, 26 Oct 2026 02:30:08 +0100
Subject: [PATCH] [mlir][spirv] Print storage class in
 spirv.INTEL.SubgroupBlockWrite

This prints the storage class which the parser requires, so the op round-trips

fixes #226050
---
 mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp           | 4 +++-
 mlir/test/Dialect/SPIRV/IR/group-ops.mlir        | 4 ++--
 mlir/test/Target/SPIRV/subgroup-block-intel.mlir | 4 ++--
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp b/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
index 35cb37a67f530a..9f445fdcba0a85 100644
--- a/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
+++ b/mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
@@ -1580,7 +1580,9 @@ ParseResult spirv::INTELSubgroupBlockWriteOp::parse(OpAsmParser &parser,
 }
 
 void spirv::INTELSubgroupBlockWriteOp::print(OpAsmPrinter &printer) {
-  printer << " " << getPtr() << ", " << getValue() << " : "
+  StringRef sc = stringifyStorageClass(
+      cast<spirv::PointerType>(getPtr().getType()).getStorageClass());
+  printer << " \"" << sc << "\" " << getPtr() << ", " << getValue() << " : "
           << getValue().getType();
 }
 
diff --git a/mlir/test/Dialect/SPIRV/IR/group-ops.mlir b/mlir/test/Dialect/SPIRV/IR/group-ops.mlir
index 7ecc57c315c4f7..df56f06339b752 100644
--- a/mlir/test/Dialect/SPIRV/IR/group-ops.mlir
+++ b/mlir/test/Dialect/SPIRV/IR/group-ops.mlir
@@ -116,7 +116,7 @@ func.func @subgroup_block_read_intel_vector(%ptr : !spirv.ptr<i32, StorageBuffer
 //===----------------------------------------------------------------------===//
 
 func.func @subgroup_block_write_intel(%ptr : !spirv.ptr<i32, StorageBuffer>, %value: i32) -> () {
-  // CHECK: spirv.INTEL.SubgroupBlockWrite %{{.*}}, %{{.*}} : i32
+  // CHECK: spirv.INTEL.SubgroupBlockWrite "StorageBuffer" %{{.*}}, %{{.*}} : i32
   spirv.INTEL.SubgroupBlockWrite "StorageBuffer" %ptr, %value : i32
   return
 }
@@ -124,7 +124,7 @@ func.func @subgroup_block_write_intel(%ptr : !spirv.ptr<i32, StorageBuffer>, %va
 // -----
 
 func.func @subgroup_block_write_intel_vector(%ptr : !spirv.ptr<i32, StorageBuffer>, %value: vector<3xi32>) -> () {
-  // CHECK: spirv.INTEL.SubgroupBlockWrite %{{.*}}, %{{.*}} : vector<3xi32>
+  // CHECK: spirv.INTEL.SubgroupBlockWrite "StorageBuffer" %{{.*}}, %{{.*}} : vector<3xi32>
   spirv.INTEL.SubgroupBlockWrite "StorageBuffer" %ptr, %value : vector<3xi32>
   return
 }
diff --git a/mlir/test/Target/SPIRV/subgroup-block-intel.mlir b/mlir/test/Target/SPIRV/subgroup-block-intel.mlir
index 14060e632fffd5..5c1079f49e4c9a 100644
--- a/mlir/test/Target/SPIRV/subgroup-block-intel.mlir
+++ b/mlir/test/Target/SPIRV/subgroup-block-intel.mlir
@@ -21,13 +21,13 @@ spirv.module Physical64 GLSL450 requires #spirv.vce<v1.3, [Addresses, Shader, Li
   }
   // CHECK-LABEL: @subgroup_block_write_intel
   spirv.func @subgroup_block_write_intel(%ptr : !spirv.ptr<i32, StorageBuffer>, %value: i32) -> () "None" {
-    // CHECK: spirv.INTEL.SubgroupBlockWrite %{{.*}}, %{{.*}} : i32
+    // CHECK: spirv.INTEL.SubgroupBlockWrite "StorageBuffer" %{{.*}}, %{{.*}} : i32
     spirv.INTEL.SubgroupBlockWrite "StorageBuffer" %ptr, %value : i32
     spirv.Return
   }
   // CHECK-LABEL: @subgroup_block_write_intel_vector
   spirv.func @subgroup_block_write_intel_vector(%ptr : !spirv.ptr<i32, StorageBuffer>, %value: vector<3xi32>) -> () "None" {
-    // CHECK: spirv.INTEL.SubgroupBlockWrite %{{.*}}, %{{.*}} : vector<3xi32>
+    // CHECK: spirv.INTEL.SubgroupBlockWrite "StorageBuffer" %{{.*}}, %{{.*}} : vector<3xi32>
     spirv.INTEL.SubgroupBlockWrite "StorageBuffer" %ptr, %value : vector<3xi32>
     spirv.Return
   }



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