[Mlir-commits] [mlir] [mlir][vector] Add i8 to i2 truncation to the narrow type rewrites (PR #221185)

[Federico Bruzzone]

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@@ -1976,6 +1976,57 @@ static Value rewriteI8ToI4Trunc(PatternRewriter &rewriter, Location loc,
   return vector::BitCastOp::create(rewriter, loc, i4VecType, mergedHiLowOp);
 }
 
+/// Rewrite the i8 -> i2 truncation into two levels of deinterleave and a
+/// series of bitwise ops to avoid leaving LLVM to scramble with peephole
+/// optimizations.
+static Value rewriteI8ToI2Trunc(PatternRewriter &rewriter, Location loc,
+                                Value srcValue) {
+  VectorType srcVecType = cast<VectorType>(srcValue.getType());
+  assert(srcVecType.getElementType().isSignlessInteger(8) &&
+         "Expected i8 type");
+
+  // 1. De-interleave twice to group the i8 elements by their position within
+  // the destination byte.
+  // in      = [0,1,2,3,4,5,6,7],...
+  // evenOdd = [0,2,4,6],... [1,3,5,7],...
+  // vec0    = [0,4],...
+  // vec1    = [1,5],...
+  // vec2    = [2,6],...
+  // vec3    = [3,7],...
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FedericoBruzzone wrote:

[nit] The comment says `vec0..vec3`, but the variables are `vec02/vec13`. Shouldn't we rename one side so they match? :D

https://github.com/llvm/llvm-project/pull/221185