[Mlir-commits] [mlir] [mlir][vector] Allow 0-D vector acc/res in `vector.contract` (PR #234638)

[Federico Bruzzone]

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@@ -340,6 +340,15 @@ func.func @extract_strided_slice_scalable(%arg0: vector<4x[8]x16xf32>) -> vector
   indexing_maps = #contraction_to_scalar_accesses,
   iterator_types = ["reduction"]
 }
+// CHECK-LABEL: @contraction_to_0d_vector
+func.func @contraction_to_0d_vector(%arg0: vector<10xf32>, %arg1: vector<10xf32>, %arg2: vector<f32>) -> vector<f32> {
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FedericoBruzzone wrote:

I'm making a mental note of this, you know, I won’t forget it! 😒

BTW, thank you! 🫶

https://github.com/llvm/llvm-project/pull/234638