[Mlir-commits] [mlir] [mlir][spirv-to-llvm] Add conversion for spirv.MemoryBarrier (PR #232939)

[Arseniy Obolenskiy]

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@@ -1385,6 +1385,62 @@ class ControlBarrierPattern : public SPIRVToLLVMConversion<BarrierOpTy> {
   }
 };
 
+/// Returns the LLVM atomic ordering denoted by the given SPIR-V memory
+/// semantics, or `std::nullopt` if the semantics set more than one ordering
+/// bit (which the SPIR-V dialect verifier rejects). Only the ordering bits
+/// (`Acquire`, `Release`, `AcquireRelease`, `SequentiallyConsistent`) are
+/// considered: the storage class bits (`UniformMemory`, `WorkgroupMemory`, ...)
+/// have no LLVM counterpart, and `MakeAvailable`/`MakeVisible` are implied by
+/// LLVM's release/acquire semantics. A semantics value with no ordering bit set
+/// is a relaxed atomic, i.e. `monotonic` in LLVM.
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aobolensk wrote:

Can we reduce comments length here as well?

https://github.com/llvm/llvm-project/pull/232939