[Mlir-commits] [mlir] [mlir][mem2reg] Support whole-buffer vector.load/store promotion (PR #224182)

[Federico Bruzzone]

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@@ -44,6 +48,30 @@ using namespace mlir::vector;
 //  Utilities
 //===----------------------------------------------------------------------===//
 
+/// Load/store accesses must cover the slot from its origin with an exactly
+/// matching vector type. The allocation or alias model determines that type.
+template <typename LoadStoreOpTy>
+static bool
+isWholeBufferLoadStore(LoadStoreOpTy op, const MemorySlot &slot,
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FedericoBruzzone wrote:

The blocking-use check and the zero-index loop duplicate `isPromotableTransfer`. Could we consider a small shared helper for the _whole slot, zero-index_ part?

https://github.com/llvm/llvm-project/pull/224182