[Mlir-commits] [mlir] [mlir][mem2reg] Support whole-buffer vector.load/store promotion (PR #224182)

[Jianhui Li]

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@@ -7,8 +7,9 @@
 //===----------------------------------------------------------------------===//
 //
 // This file implements memory slot interface models for
-// `vector.transfer_read` and `vector.transfer_write`. These models implement
-// `PromotableMemOpInterface` so Mem2Reg can replace vector transfers with uses
+// `vector.load`, `vector.store`, `vector.transfer_read`, and
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Jianhui-Li wrote:

nit: could align the text so each line has similar number of characters.

https://github.com/llvm/llvm-project/pull/224182