[Mlir-commits] [mlir] [mlir][NVVM] Lower vector<1xf32> nvvm.ex2 through the scalar intrinsic (PR #231517)
Bastian Hagedorn
llvmlistbot at llvm.org
Fri Oct 16 00:51:40 PDT 2026
================
@@ -516,6 +517,23 @@ def NVVM_Ex2Op
$src oilist(`ftz` `=` $ftz) attr-dict `:` type($src)
}];
let hasVerifier = 1;
+ let llvmBuilder = [{
+ auto [id, args] =
+ NVVM::Ex2Op::getIntrinsicIDAndArgs(*op, moduleTranslation, builder);
+ llvm::Value *src = args[0];
+ auto *vecTy = llvm::dyn_cast<llvm::FixedVectorType>(src->getType());
+ if (vecTy && vecTy->getNumElements() == 1) {
+ // There is no one-lane PTX form; use the scalar f32 intrinsic.
+ llvm::Value *lane = builder.CreateExtractElement(src, builder.getInt32(0));
----------------
bastianhagedorn wrote:
Good call, switched to bitcasts in 6ab28ab.
https://github.com/llvm/llvm-project/pull/231517
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