[Mlir-commits] [llvm] [mlir] [mlir] `HasParallelRegion` means region may be parallel (PR #231372)

[Matteo Di Iorio]

splicer3 wrote:

This should fix #226090. I had considered adding the trait unconditionally there, but I was concerned about also blocking hoisting from `acc.loop seq`. I think treating that conservatively for now makes sense, especially considering potential future work to turn the trait into an op interface.

With this PR applied on top of main containing #226951 I found two tests in `buffer-loop-hoisting.mlir` that need their expectations updated:

- `hoist_sequential_acc_loop` expects the allocation to move before `acc.loop seq`, but now it stays inside.
- `no_hoist_while_parallel_acc_parent` expects the allocation to stay inside `scf.while`, but now it moves before the `while` and still remains inside `acc.loop`.

The second case also removes the limitation we kept for this `acc` parent in #226951 since it now provides a parallel boundary.

https://github.com/llvm/llvm-project/pull/231372