[Mlir-commits] [mlir] [mlir][doc] Document FP8 e4m3/e5m2 mma.sync formats (PR #211841)

[Vito Secona]

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@@ -3415,6 +3417,8 @@ def NVVM_MmaOp : NVVM_Op<"mma.sync", [AttrSizedOperandSegments]> {
     |          | m16n8k64  | row     | col     | 4x i32   | 2x i32   | 4x i32            |
     | b1       | m8n8k128  | row     | col     | 1x i32   | 1x i32   | 2x i32            |
     |          | m16n8k128 | row     | col     | 2x i32   | 1x i32   | 4x i32            |
+    | e4m3/e5m2 | .m16n8k16 | row     | col     | 2x i32   | 1x i32   | 2x f16x2 or 4 f32 |
+    |            | .m16n8k32 | row     | col     | 4x i32   | 2x i32   | 2x f16x2 or 4 f32 |
     ```
 
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secona wrote:

Its also worth to direct readers to the PTX ISA docs like so. Thoughts?

```suggestion
    [For more information, see PTX ISA](https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#warp-level-matrix-shape)
```

https://github.com/llvm/llvm-project/pull/211841