[Mlir-commits] [mlir] [mlir][tosa] Add MXFP support for CONV3D (PR #230148)
llvmlistbot at llvm.org
llvmlistbot at llvm.org
Thu Oct 8 07:51:20 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-mlir-tosa
Author: Deeptanshu Sekhri (deeptanshusekhri)
<details>
<summary>Changes</summary>
Extend CONV3D compliance entries for MXFP operands.
Add MXFP validation tests.
---
Patch is 88.90 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/230148.diff
7 Files Affected:
- (modified) mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc (+1349-2)
- (modified) mlir/test/Dialect/Tosa/invalid.mlir (+20)
- (modified) mlir/test/Dialect/Tosa/invalid_extension.mlir (+20)
- (modified) mlir/test/Dialect/Tosa/ops.mlir (+12)
- (modified) mlir/test/Dialect/Tosa/tosa-validation-version-1p0-invalid.mlir (+20)
- (modified) mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir (+120)
- (modified) mlir/test/Dialect/Tosa/verifier.mlir (+20)
``````````diff
diff --git a/mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc b/mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
index e3789986735fa..9d14003d72e0b 100644
--- a/mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
+++ b/mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc
@@ -55,7 +55,13 @@ profileComplianceMap = {
{{fp16T, fp16T, fp16T, fp16T, fp16T, fp32T, fp16T},
SpecificationVersion::V_1_0},
{{fp32T, fp32T, fp32T, fp32T, fp32T, fp32T, fp32T},
- SpecificationVersion::V_1_0}}}}},
+ SpecificationVersion::V_1_0},
+ {{fp16T, fp16T, fp32T, fp16T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, fp32T, fp32T, fp16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, fp16T, fp32T, fp32T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}}}}},
{"tosa.depthwise_conv2d",
{{{Profile::pro_int},
{{{i8T, i8T, i32T, i8T, i8T, i32T, i32T}, SpecificationVersion::V_1_0}}},
@@ -2029,16 +2035,1357 @@ extensionComplianceMap = {
{{Extension::fp8e4m3},
{{{fp8e4m3T, fp8e4m3T, fp16T, fp8e4m3T, fp8e4m3T, fp16T, fp16T},
SpecificationVersion::V_1_0},
+ {{fp8e4m3T, fp8e4m3T, fp16T, fp8e4m3T, fp8e4m3T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp8e4m3T, fp16T, fp8e4m3T, fp8e4m3T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp16T, fp16T, fp8e4m3T, fp16T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp16T, fp16T, fp8e4m3T, fp16T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, fp8e4m3T, fp16T, fp16T, fp8e4m3T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, fp8e4m3T, fp16T, fp16T, fp8e4m3T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
{{fp8e4m3T, fp8e4m3T, fp32T, fp8e4m3T, fp8e4m3T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, fp8e4m3T, fp32T, fp16T, fp8e4m3T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T, fp32T},
SpecificationVersion::V_1_1_DRAFT}}},
{{Extension::fp8e5m2},
{{{fp8e5m2T, fp8e5m2T, fp16T, fp8e5m2T, fp8e5m2T, fp16T, fp16T},
SpecificationVersion::V_1_0},
+ {{fp8e5m2T, fp8e5m2T, fp16T, fp8e5m2T, fp8e5m2T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp8e5m2T, fp16T, fp8e5m2T, fp8e5m2T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp16T, fp16T, fp8e5m2T, fp16T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp16T, fp16T, fp8e5m2T, fp16T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, fp8e5m2T, fp16T, fp16T, fp8e5m2T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, fp8e5m2T, fp16T, fp16T, fp8e5m2T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
{{fp8e5m2T, fp8e5m2T, fp32T, fp8e5m2T, fp8e5m2T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, fp8e5m2T, fp32T, fp16T, fp8e5m2T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T, fp32T},
SpecificationVersion::V_1_1_DRAFT}}},
{{Extension::bf16},
{{{bf16T, bf16T, bf16T, bf16T, bf16T, fp32T, bf16T},
- SpecificationVersion::V_1_0}}}}},
+ SpecificationVersion::V_1_0},
+ {{bf16T, bf16T, bf16T, bf16T, bf16T, bf16T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, bf16T, bf16T, bf16T, bf16T, fp32T, bf16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bf16T, fp32T, fp16T, bf16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, fp16T, fp32T, bf16T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, bf16T, fp32T, bf16T, bf16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bf16T, fp32T, fp32T, bf16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, bf16T, fp32T, fp32T, bf16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}}},
+ {{Extension::fp8e4m3, Extension::fp8e5m2},
+ {{{fp8e4m3T, fp8e5m2T, fp16T, fp8e4m3T, fp8e5m2T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp8e5m2T, fp16T, fp8e4m3T, fp8e5m2T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp8e4m3T, fp16T, fp8e5m2T, fp8e4m3T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp8e4m3T, fp16T, fp8e5m2T, fp8e4m3T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, fp8e5m2T, fp32T, fp8e4m3T, fp8e5m2T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, fp8e4m3T, fp32T, fp8e5m2T, fp8e4m3T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e4m3, Extension::mx_common, Extension::mx_fp8e4m3},
+ {{{fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp8e4m3T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp8e4m3T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, fp32T, fp8e4m3T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e4m3, Extension::mx_common, Extension::mx_fp8e5m2},
+ {{{fp8e4m3T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp8e4m3T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp8e4m3T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp8e5m2T, fp32T, fp8e4m3T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e4m3, Extension::mx_common, Extension::mx_fp6e3m2},
+ {{{fp8e4m3T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp8e4m3T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp8e4m3T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp6e3m2T, fp32T, fp8e4m3T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e4m3, Extension::mx_common, Extension::mx_fp6e2m3},
+ {{{fp8e4m3T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp8e4m3T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp8e4m3T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp6e2m3T, fp32T, fp8e4m3T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e4m3, Extension::mx_common, Extension::mx_fp4e2m1},
+ {{{fp8e4m3T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp8e4m3T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp8e4m3T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_fp4e2m1T, fp32T, fp8e4m3T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e4m3, Extension::mx_common, Extension::mx_int8},
+ {{{fp8e4m3T, bs32_fp8ue8m0_mxint8T, fp16T, fp8e4m3T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_mxint8T, fp16T, fp8e4m3T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e4m3T, fp16T, fp32T, fp8e4m3T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e4m3T, bs32_fp8ue8m0_mxint8T, fp32T, fp8e4m3T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e4m3T, fp32T, fp32T, fp8e4m3T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e5m2, Extension::mx_common, Extension::mx_fp8e4m3},
+ {{{fp8e5m2T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp8e5m2T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp8e5m2T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp8e4m3T, fp32T, fp8e5m2T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e5m2, Extension::mx_common, Extension::mx_fp8e5m2},
+ {{{fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp8e5m2T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp8e5m2T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, fp32T, fp8e5m2T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e5m2, Extension::mx_common, Extension::mx_fp6e3m2},
+ {{{fp8e5m2T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp8e5m2T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp8e5m2T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp6e3m2T, fp32T, fp8e5m2T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e5m2, Extension::mx_common, Extension::mx_fp6e2m3},
+ {{{fp8e5m2T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp8e5m2T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp6e2m3T, fp16T, fp8e5m2T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp6e2m3T, fp32T, fp8e5m2T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e2m3T, fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e5m2, Extension::mx_common, Extension::mx_fp4e2m1},
+ {{{fp8e5m2T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp8e5m2T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp4e2m1T, fp16T, fp8e5m2T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_fp4e2m1T, fp32T, fp8e5m2T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp4e2m1T, fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::fp8e5m2, Extension::mx_common, Extension::mx_int8},
+ {{{fp8e5m2T, bs32_fp8ue8m0_mxint8T, fp16T, fp8e5m2T, fp32T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_mxint8T, fp16T, fp8e5m2T, fp32T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp16T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e5m2T, fp16T, fp32T, fp8e5m2T, fp32T,
+ fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp8e5m2T, bs32_fp8ue8m0_mxint8T, fp32T, fp8e5m2T, fp32T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_mxint8T, fp8e5m2T, fp32T, fp32T, fp8e5m2T, fp32T,
+ fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp8e4m3},
+ {{{fp16T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp16T, fp32T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp16T, fp32T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp16T, fp16T, fp32T, fp16T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp16T, fp16T, fp32T, fp16T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_fp8e4m3T, fp32T, fp16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, bs32_fp8ue8m0_fp8e4m3T, fp32T, fp32T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp16T, fp32T, fp32T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, fp32T, fp32T, fp32T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e4m3T, bs32_fp8ue8m0_fp8e4m3T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp8e5m2},
+ {{{fp16T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp16T, fp32T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp16T, fp32T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp16T, fp16T, fp32T, fp16T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp16T, fp16T, fp32T, fp16T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp32T, fp32T,
+ fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, fp16T, fp32T, fp32T,
+ fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_fp8e5m2T, fp32T, fp16T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp32T, bs32_fp8ue8m0_fp8e5m2T, fp32T, fp32T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp16T, fp32T, fp32T, fp16T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, fp32T, fp32T, fp32T, fp32T, fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp8e5m2T, bs32_fp8ue8m0_fp8e5m2T, fp32T, fp32T, fp32T,
+ fp32T, fp32T},
+ SpecificationVersion::V_1_1_DRAFT}},
+ allOf},
+ {{Extension::mx_common, Extension::mx_fp6e3m2},
+ {{{fp16T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp16T, fp32T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{fp16T, bs32_fp8ue8m0_fp6e3m2T, fp16T, fp16T, fp32T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp16T, fp16T, fp32T, fp16T, fp16T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue8m0_fp6e3m2T, fp16T, fp16T, fp32T, fp16T, fp32T, fp16T},
+ SpecificationVersion::V_1_1_DRAFT},
+ {{bs32_fp8ue...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/230148
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