[Mlir-commits] [mlir] e31aed1 - [mlir][tosa] Allow i64 accumulators (#228427)

llvmlistbot at llvm.org llvmlistbot at llvm.org
Mon Oct 5 01:39:02 PDT 2026


Author: Michael Platings
Date: 2026-10-05T09:38:54+01:00
New Revision: e31aed1b32731915578b5617cd32e1c0b311365d

URL: https://github.com/llvm/llvm-project/commit/e31aed1b32731915578b5617cd32e1c0b311365d
DIFF: https://github.com/llvm/llvm-project/commit/e31aed1b32731915578b5617cd32e1c0b311365d.diff

LOG: [mlir][tosa] Allow i64 accumulators (#228427)

This can be helpful for incremental lowerings to/from TOSA.

Added: 
    

Modified: 
    mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
    mlir/test/Dialect/Tosa/ops.mlir

Removed: 
    


################################################################################
diff  --git a/mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td b/mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
index 8b5803c3074f0..339061b2aee83 100644
--- a/mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
+++ b/mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
@@ -103,7 +103,7 @@ def Tosa_ArgMinOp : Tosa_InferShapedTypeOp<"argmin", [NoMemoryEffect]> {
 // Accumulator types.
 //===----------------------------------------------------------------------===//
 
-def Tosa_AccType : AnyTypeOf<[I<32>, I<48>, F16, F32, BF16]>;
+def Tosa_AccType : AnyTypeOf<[I<32>, I<48>, I<64>, F16, F32, BF16]>;
 
 //===----------------------------------------------------------------------===//
 // Operator: avg_pool2d

diff  --git a/mlir/test/Dialect/Tosa/ops.mlir b/mlir/test/Dialect/Tosa/ops.mlir
index 2592b08b35d39..9f2b7f1e5ee1e 100644
--- a/mlir/test/Dialect/Tosa/ops.mlir
+++ b/mlir/test/Dialect/Tosa/ops.mlir
@@ -149,6 +149,15 @@ func.func @test_conv2d(%arg0: tensor<1x4x4x4xf32>, %arg1: tensor<8x1x1x4xf32>, %
   return %0 : tensor<1x4x4x8xf32>
 }
 
+// -----
+// Allow i64 accumulators to facilitate incremental lowerings to/from TOSA.
+// CHECK-LABEL: conv2d_i64
+// CHECK: acc_type(i64)
+func.func @test_conv2d_i64(%input: tensor<1x1x1x1xi16>, %weight: tensor<1x1x1x1xi8>, %bias: tensor<1xi64>, %izp: tensor<1xi16>, %wzp: tensor<1xi8>) -> tensor<1x1x1x1xi64> {
+  %0 = tosa.conv2d %input, %weight, %bias, %izp, %wzp pad([0, 0, 0, 0]) stride([1, 1]) dilation([1, 1]) acc_type(i64) : (tensor<1x1x1x1xi16>, tensor<1x1x1x1xi8>, tensor<1xi64>, tensor<1xi16>, tensor<1xi8>) -> tensor<1x1x1x1xi64>
+  return %0 : tensor<1x1x1x1xi64>
+}
+
 // -----
 // CHECK-LABEL: conv2d_mxfp
 func.func @test_conv2d_mxfp(%arg0: tensor<1x4x4x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, %arg1: tensor<8x1x1x32x!tosa.block_scaled<BLOCK_SHAPE_32:f8E8M0FNU:f4E2M1FN>>, %arg2: tensor<8xf16>) -> tensor<1x4x4x8xf16> {


        


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