[Mlir-commits] [mlir] [mlir][SPIR-V] Verify memory semantics for AtomicLoad/Store/Exchange/CompareExchange ops (PR #212990)
Arseniy Obolenskiy
llvmlistbot at llvm.org
Thu Oct 1 01:24:16 PDT 2026
https://github.com/aobolensk updated https://github.com/llvm/llvm-project/pull/212990
>From c6e6db6a3165bb072073a0581a0c9b1563fa2fbe Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Thu, 30 Jul 2026 12:38:22 +0200
Subject: [PATCH 1/2] [mlir][SPIR-V] Verify memory semantics for
AtomicLoad/Store/Exchange/CompareExchange ops
---
.../mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td | 5 ---
mlir/lib/Dialect/SPIRV/IR/AtomicOps.cpp | 44 +++++++++++++++++++
mlir/test/Dialect/SPIRV/IR/atomic-ops.mlir | 40 +++++++++++++++++
3 files changed, 84 insertions(+), 5 deletions(-)
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td
index d756a923b744f..c706e39c4eb0c 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td
@@ -172,7 +172,6 @@ def SPIRV_AtomicCompareExchangeOp : SPIRV_Op<"AtomicCompareExchange", [
}];
let hasCustomAssemblyFormat = 0;
- let hasVerifier = 0;
}
// -----
@@ -226,7 +225,6 @@ def SPIRV_AtomicCompareExchangeWeakOp : SPIRV_Op<"AtomicCompareExchangeWeak", [
}];
let hasCustomAssemblyFormat = 0;
- let hasVerifier = 0;
}
// -----
@@ -272,7 +270,6 @@ def SPIRV_AtomicLoadOp : SPIRV_Op<"AtomicLoad", [
}];
let hasCustomAssemblyFormat = 0;
- let hasVerifier = 0;
}
// -----
@@ -315,7 +312,6 @@ def SPIRV_AtomicStoreOp : SPIRV_Op<"AtomicStore", [
}];
let hasCustomAssemblyFormat = 0;
- let hasVerifier = 0;
}
// -----
@@ -371,7 +367,6 @@ def SPIRV_AtomicExchangeOp : SPIRV_Op<"AtomicExchange", [
}];
let hasCustomAssemblyFormat = 0;
- let hasVerifier = 0;
}
// -----
diff --git a/mlir/lib/Dialect/SPIRV/IR/AtomicOps.cpp b/mlir/lib/Dialect/SPIRV/IR/AtomicOps.cpp
index 7029268177128..b88bdbe7af730 100644
--- a/mlir/lib/Dialect/SPIRV/IR/AtomicOps.cpp
+++ b/mlir/lib/Dialect/SPIRV/IR/AtomicOps.cpp
@@ -61,6 +61,50 @@ LogicalResult AtomicAndOp::verify() {
return verifyAtomicUpdateOp<AtomicAndOp, IntegerType>(getOperation());
}
+//===----------------------------------------------------------------------===//
+// spirv.AtomicCompareExchangeOp
+//===----------------------------------------------------------------------===//
+
+LogicalResult AtomicCompareExchangeOp::verify() {
+ if (failed(verifyMemorySemantics(getOperation(), getEqualSemantics())))
+ return failure();
+ return verifyMemorySemantics(getOperation(), getUnequalSemantics());
+}
+
+//===----------------------------------------------------------------------===//
+// spirv.AtomicCompareExchangeWeakOp
+//===----------------------------------------------------------------------===//
+
+LogicalResult AtomicCompareExchangeWeakOp::verify() {
+ if (failed(verifyMemorySemantics(getOperation(), getEqualSemantics())))
+ return failure();
+ return verifyMemorySemantics(getOperation(), getUnequalSemantics());
+}
+
+//===----------------------------------------------------------------------===//
+// spirv.AtomicExchangeOp
+//===----------------------------------------------------------------------===//
+
+LogicalResult AtomicExchangeOp::verify() {
+ return verifyMemorySemantics(getOperation(), getSemantics());
+}
+
+//===----------------------------------------------------------------------===//
+// spirv.AtomicLoadOp
+//===----------------------------------------------------------------------===//
+
+LogicalResult AtomicLoadOp::verify() {
+ return verifyMemorySemantics(getOperation(), getSemantics());
+}
+
+//===----------------------------------------------------------------------===//
+// spirv.AtomicStoreOp
+//===----------------------------------------------------------------------===//
+
+LogicalResult AtomicStoreOp::verify() {
+ return verifyMemorySemantics(getOperation(), getSemantics());
+}
+
//===----------------------------------------------------------------------===//
// spirv.AtomicIAddOp
//===----------------------------------------------------------------------===//
diff --git a/mlir/test/Dialect/SPIRV/IR/atomic-ops.mlir b/mlir/test/Dialect/SPIRV/IR/atomic-ops.mlir
index feaa9123fd715..7ca5975754c50 100644
--- a/mlir/test/Dialect/SPIRV/IR/atomic-ops.mlir
+++ b/mlir/test/Dialect/SPIRV/IR/atomic-ops.mlir
@@ -73,6 +73,14 @@ func.func @atomic_compare_exchange(%ptr: !spirv.ptr<i64, Workgroup>, %value: i32
// -----
+func.func @atomic_compare_exchange(%ptr: !spirv.ptr<i32, Workgroup>, %value: i32, %comparator: i32) -> i32 {
+ // expected-error @+1 {{expected at most one of these four memory constraints to be set: `Acquire`, `Release`,`AcquireRelease` or `SequentiallyConsistent`}}
+ %0 = spirv.AtomicCompareExchange <Workgroup> <Acquire|Release> <None> %ptr, %value, %comparator: !spirv.ptr<i32, Workgroup>
+ return %0: i32
+}
+
+// -----
+
//===----------------------------------------------------------------------===//
// spirv.AtomicCompareExchangeWeak
//===----------------------------------------------------------------------===//
@@ -109,6 +117,14 @@ func.func @atomic_compare_exchange_weak(%ptr: !spirv.ptr<i64, Workgroup>, %value
// -----
+func.func @atomic_compare_exchange_weak(%ptr: !spirv.ptr<i32, Workgroup>, %value: i32, %comparator: i32) -> i32 {
+ // expected-error @+1 {{expected at most one of these four memory constraints to be set: `Acquire`, `Release`,`AcquireRelease` or `SequentiallyConsistent`}}
+ %0 = spirv.AtomicCompareExchangeWeak <Workgroup> <Acquire|Release> <None> %ptr, %value, %comparator: !spirv.ptr<i32, Workgroup>
+ return %0: i32
+}
+
+// -----
+
//===----------------------------------------------------------------------===//
// spirv.AtomicExchange
//===----------------------------------------------------------------------===//
@@ -153,6 +169,14 @@ func.func @atomic_exchange(%ptr: !spirv.ptr<i64, Workgroup>, %value: i32) -> i32
// -----
+func.func @atomic_exchange(%ptr: !spirv.ptr<i32, Workgroup>, %value: i32) -> i32 {
+ // expected-error @+1 {{expected at most one of these four memory constraints to be set: `Acquire`, `Release`,`AcquireRelease` or `SequentiallyConsistent`}}
+ %0 = spirv.AtomicExchange <Workgroup> <Acquire|Release> %ptr, %value: !spirv.ptr<i32, Workgroup>
+ return %0: i32
+}
+
+// -----
+
//===----------------------------------------------------------------------===//
// spirv.AtomicIAdd
//===----------------------------------------------------------------------===//
@@ -223,6 +247,14 @@ func.func @atomic_load_mismatch(%ptr : !spirv.ptr<i32, Workgroup>) -> i64 {
// -----
+func.func @atomic_load(%ptr : !spirv.ptr<i32, Workgroup>) -> i32 {
+ // expected-error @+1 {{expected at most one of these four memory constraints to be set: `Acquire`, `Release`,`AcquireRelease` or `SequentiallyConsistent`}}
+ %0 = spirv.AtomicLoad <Workgroup> <Acquire|Release> %ptr : !spirv.ptr<i32, Workgroup>
+ return %0 : i32
+}
+
+// -----
+
//===----------------------------------------------------------------------===//
// spirv.AtomicOr
//===----------------------------------------------------------------------===//
@@ -283,6 +315,14 @@ func.func @atomic_store_mismatch(%ptr : !spirv.ptr<i32, Workgroup>, %value : i64
// -----
+func.func @atomic_store(%ptr : !spirv.ptr<i32, Workgroup>, %value : i32) {
+ // expected-error @+1 {{expected at most one of these four memory constraints to be set: `Acquire`, `Release`,`AcquireRelease` or `SequentiallyConsistent`}}
+ spirv.AtomicStore <Workgroup> <Acquire|Release> %ptr, %value : !spirv.ptr<i32, Workgroup>
+ return
+}
+
+// -----
+
//===----------------------------------------------------------------------===//
// spirv.AtomicUMax
//===----------------------------------------------------------------------===//
>From 6a366aa57e8f715cd1f4eaac29f7e91b3d89a121 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Thu, 1 Oct 2026 10:23:58 +0200
Subject: [PATCH 2/2] test
---
mlir/test/Dialect/SPIRV/IR/atomic-ops.mlir | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/mlir/test/Dialect/SPIRV/IR/atomic-ops.mlir b/mlir/test/Dialect/SPIRV/IR/atomic-ops.mlir
index 7ca5975754c50..8fb91617aa2fe 100644
--- a/mlir/test/Dialect/SPIRV/IR/atomic-ops.mlir
+++ b/mlir/test/Dialect/SPIRV/IR/atomic-ops.mlir
@@ -81,6 +81,14 @@ func.func @atomic_compare_exchange(%ptr: !spirv.ptr<i32, Workgroup>, %value: i32
// -----
+func.func @atomic_compare_exchange_unequal(%ptr: !spirv.ptr<i32, Workgroup>, %value: i32, %comparator: i32) -> i32 {
+ // expected-error @+1 {{expected at most one of these four memory constraints to be set: `Acquire`, `Release`,`AcquireRelease` or `SequentiallyConsistent`}}
+ %0 = spirv.AtomicCompareExchange <Workgroup> <None> <Acquire|Release> %ptr, %value, %comparator: !spirv.ptr<i32, Workgroup>
+ return %0: i32
+}
+
+// -----
+
//===----------------------------------------------------------------------===//
// spirv.AtomicCompareExchangeWeak
//===----------------------------------------------------------------------===//
@@ -125,6 +133,14 @@ func.func @atomic_compare_exchange_weak(%ptr: !spirv.ptr<i32, Workgroup>, %value
// -----
+func.func @atomic_compare_exchange_weak_unequal(%ptr: !spirv.ptr<i32, Workgroup>, %value: i32, %comparator: i32) -> i32 {
+ // expected-error @+1 {{expected at most one of these four memory constraints to be set: `Acquire`, `Release`,`AcquireRelease` or `SequentiallyConsistent`}}
+ %0 = spirv.AtomicCompareExchangeWeak <Workgroup> <None> <Acquire|Release> %ptr, %value, %comparator: !spirv.ptr<i32, Workgroup>
+ return %0: i32
+}
+
+// -----
+
//===----------------------------------------------------------------------===//
// spirv.AtomicExchange
//===----------------------------------------------------------------------===//
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