[Mlir-commits] [clang] [llvm] [mlir] [AMDGPU] Implement AsyncMark Stages (PR #220442)

[Sameer Sahasrabuddhe]

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@@ -1091,9 +1065,9 @@ void WaitcntBrackets::updateByEvent(HWEvents E, MachineInstr &Inst) {
         setVMemScore(LDSDMA_BEGIN + static_cast<VMEMID>(Slot), T, CurrScore);
     }
 
-    if (Context->shouldUpdateAsyncMark(Inst, T)) {
-      AsyncScore[T] = CurrScore;
-    }
+    AMDGPU::AsyncStages Stage = TII.getAsyncStage(Inst);
+    if (any(Stage))
+      AsyncScore[AMDGPU::getAsyncStageIndex(Stage)][T] = CurrScore;
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ssahasra wrote:

So `AsyncScore` is now a 2-D grid with one cell for every  combination of Stage and Counter. Is there no need for constraining which cells must remain zero? The deleted lines check if the score `T` should be updated for the given inst, but now there is no such check.

In particular, if `Inst` maps to a stage `FOO`, and the value of `T` is `BAR_CNT`, should the entry happen only if `BAR_CNT` is actually relevant to `FOO`? If the score for `BAR_CNT` is updated unconditionally, can it result in an unnecessary wait?

https://github.com/llvm/llvm-project/pull/220442