[Mlir-commits] [mlir] [mlir][vector] Consistently name Vector op results (PR #238070)
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llvmlistbot at llvm.org
Mon Nov 2 11:03:08 PST 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-mlir-gpu
@llvm/pr-subscribers-mlir
Author: Andrzej Warzyński (banach-space)
<details>
<summary>Changes</summary>
This continues the cleanup tracked in #<!-- -->131602.
Use result consistently in Vector op definitions, replacing names such
as dest and res. For DeinterleaveOp, rename res1 and res2 to resultEven
and resultOdd, respectively, to reflect their contents.
---
Patch is 30.45 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/238070.diff
14 Files Affected:
- (modified) mlir/include/mlir/Dialect/Vector/IR/VectorOps.td (+13-13)
- (modified) mlir/lib/Dialect/ArmSVE/Transforms/LowerContractToSVEPatterns.cpp (+4-4)
- (modified) mlir/lib/Dialect/Vector/IR/VectorOps.cpp (+8-8)
- (modified) mlir/lib/Dialect/Vector/Transforms/LowerVectorInterleave.cpp (+2-2)
- (modified) mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp (+3-3)
- (modified) mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp (+2-2)
- (modified) mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToLaneDistribute.cpp (+2-2)
- (modified) mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp (+2-2)
- (modified) mlir/test/Dialect/Vector/CPU/ArmSVE/vector-bfmmla.mlir (+6-6)
- (modified) mlir/test/Dialect/Vector/CPU/ArmSVE/vector-smmla.mlir (+12-12)
- (modified) mlir/test/Dialect/Vector/CPU/ArmSVE/vector-summla.mlir (+2-2)
- (modified) mlir/test/Dialect/Vector/CPU/ArmSVE/vector-ummla.mlir (+6-6)
- (modified) mlir/test/Dialect/Vector/CPU/ArmSVE/vector-usmmla.mlir (+6-6)
- (modified) mlir/test/Dialect/Vector/invalid.mlir (+3-3)
``````````diff
diff --git a/mlir/include/mlir/Dialect/Vector/IR/VectorOps.td b/mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
index db422ceb086c37..61c28f9d9176fe 100644
--- a/mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
+++ b/mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
@@ -328,7 +328,7 @@ def Vector_ReductionOp :
def Vector_MultiDimReductionOp :
Vector_Op<"multi_reduction", [Pure,
- AllTypesMatch<["dest", "acc"]>,
+ AllTypesMatch<["result", "acc"]>,
PredOpTrait<"source operand and result have same element type",
TCresVTEtIsSameAsOpBase<0, 0>>,
DeclareOpInterfaceMethods<ArithFastMathInterface>,
@@ -343,7 +343,7 @@ def Vector_MultiDimReductionOp :
DefaultValuedAttr<
Arith_FastMathAttr,
"::mlir::arith::FastMathFlags::none">:$fastmath)>,
- Results<(outs AnyType:$dest)> {
+ Results<(outs AnyType:$result)> {
let summary = "Multi-dimensional reduction operation";
let description = [{
Reduces an n-D vector into an (n-k)-D vector (or a scalar when k == n)
@@ -382,7 +382,7 @@ def Vector_MultiDimReductionOp :
return ::llvm::cast<VectorType>(getSource().getType());
}
Type getDestType() {
- return getDest().getType();
+ return getResult().getType();
}
bool isReducedDim(int64_t d) {
@@ -407,7 +407,7 @@ def Vector_MultiDimReductionOp :
}];
let assemblyFormat =
"$kind `,` $source `,` $acc (`fastmath` `` $fastmath^)? attr-dict "
- "$reduction_dims `:` type($source) `to` type($dest)";
+ "$reduction_dims `:` type($source) `to` type($result)";
let hasFolder = 1;
let hasCanonicalizer = 1;
let hasVerifier = 1;
@@ -666,8 +666,8 @@ def SourceVectorEvenElementCount : PredOpTrait<
def Vector_DeinterleaveOp :
Vector_Op<"deinterleave", [Pure,
SourceVectorEvenElementCount,
- ResultIsHalfSourceVectorType<"res1">,
- AllTypesMatch<["res1", "res2"]>,
+ ResultIsHalfSourceVectorType<"resultEven">,
+ AllTypesMatch<["resultEven", "resultOdd"]>,
DeclareOpInterfaceMethods<VectorUnrollOpInterface, ["getIterationShapeToUnroll"]>
]> {
let summary = "constructs two vectors by deinterleaving an input vector";
@@ -702,10 +702,10 @@ def Vector_DeinterleaveOp :
}];
let arguments = (ins AnyVectorOfNonZeroRank:$source);
- let results = (outs AnyVectorOfNonZeroRank:$res1, AnyVectorOfNonZeroRank:$res2);
+ let results = (outs AnyVectorOfNonZeroRank:$resultEven, AnyVectorOfNonZeroRank:$resultOdd);
let assemblyFormat = [{
- $source attr-dict `:` type($source) `->` type($res1)
+ $source attr-dict `:` type($source) `->` type($resultEven)
}];
let extraClassDeclaration = [{
@@ -713,7 +713,7 @@ def Vector_DeinterleaveOp :
return ::llvm::cast<VectorType>(getSource().getType());
}
VectorType getResultVectorType() {
- return ::llvm::cast<VectorType>(getRes1().getType());
+ return ::llvm::cast<VectorType>(getResultEven().getType());
}
}];
}
@@ -877,7 +877,7 @@ def Vector_ToElementsOp : Vector_Op<"to_elements", [
def Vector_FromElementsOp : Vector_Op<"from_elements", [
Pure,
- ShapedTypeMatchesElementCountAndTypes<"dest", "elements">]> {
+ ShapedTypeMatchesElementCountAndTypes<"result", "elements">]> {
let summary = "operation that defines a vector from scalar elements";
let description = [{
This operation defines a vector from one or multiple scalar elements. The
@@ -908,8 +908,8 @@ def Vector_FromElementsOp : Vector_Op<"from_elements", [
}];
let arguments = (ins Variadic<AnyType>:$elements);
- let results = (outs AnyFixedVectorOfAnyRank:$dest);
- let assemblyFormat = "$elements attr-dict `:` type($dest)";
+ let results = (outs AnyFixedVectorOfAnyRank:$result);
+ let assemblyFormat = "$elements attr-dict `:` type($result)";
let hasFolder = 1;
let hasCanonicalizer = 1;
}
@@ -3051,7 +3051,7 @@ def VectorScaleOp : Vector_Op<"vscale",
Right now we only support one contiguous set of scalable dimensions, all of
them grouped and scaled with the value returned by 'vscale'.
}];
- let results = (outs Index:$res);
+ let results = (outs Index:$result);
let assemblyFormat = "attr-dict";
let extraClassDefinition = [{
diff --git a/mlir/lib/Dialect/ArmSVE/Transforms/LowerContractToSVEPatterns.cpp b/mlir/lib/Dialect/ArmSVE/Transforms/LowerContractToSVEPatterns.cpp
index 1c82297a9e0c0f..b01415f0980a87 100644
--- a/mlir/lib/Dialect/ArmSVE/Transforms/LowerContractToSVEPatterns.cpp
+++ b/mlir/lib/Dialect/ArmSVE/Transforms/LowerContractToSVEPatterns.cpp
@@ -401,8 +401,8 @@ Value VectorContractRewriter::lower(vector::ContractionOp op,
Value out0, out1;
if (swapOperands) {
auto tmp = vector::DeinterleaveOp::create(rewriter, loc, row);
- out0 = tmp.getRes1();
- out1 = tmp.getRes2();
+ out0 = tmp.getResultEven();
+ out1 = tmp.getResultOdd();
} else {
// Deinterleave by pairs.
auto row64 = vector::BitCastOp::create(rewriter, loc, accRowX264Ty, row);
@@ -410,9 +410,9 @@ Value VectorContractRewriter::lower(vector::ContractionOp op,
// Bitcast back into original element type and insert into the result.
out0 = vector::BitCastOp::create(rewriter, loc, accRowTy,
- deintr64.getRes1());
+ deintr64.getResultEven());
out1 = vector::BitCastOp::create(rewriter, loc, accRowTy,
- deintr64.getRes2());
+ deintr64.getResultOdd());
}
result = vector::InsertOp::create(rewriter, loc, out0, result, i * 2);
result = vector::InsertOp::create(rewriter, loc, out1, result, i * 2 + 1);
diff --git a/mlir/lib/Dialect/Vector/IR/VectorOps.cpp b/mlir/lib/Dialect/Vector/IR/VectorOps.cpp
index 7945ca3ea79634..be34a5e95ee2ac 100644
--- a/mlir/lib/Dialect/Vector/IR/VectorOps.cpp
+++ b/mlir/lib/Dialect/Vector/IR/VectorOps.cpp
@@ -755,7 +755,7 @@ LogicalResult ReductionOp::verify() {
return emitOpError("unsupported reduction rank: ") << rank;
// Verify supported reduction kind.
- Type eltType = getDest().getType();
+ Type eltType = getResult().getType();
if (!isSupportedCombiningKind(getKind(), eltType))
return emitOpError("unsupported reduction type '")
<< eltType << "' for kind '" << stringifyCombiningKind(getKind())
@@ -2883,18 +2883,18 @@ static OpFoldResult foldFromElementsToConstant(FromElementsOp fromElementsOp,
return {};
// DenseElementsAttr only supports int/index/float/complex types.
- auto destVecType = fromElementsOp.getDest().getType();
- auto destEltType = destVecType.getElementType();
- if (!destEltType.isIntOrIndexOrFloat() && !isa<ComplexType>(destEltType))
+ auto resVecType = fromElementsOp.getResult().getType();
+ auto resEltType = resVecType.getElementType();
+ if (!resEltType.isIntOrIndexOrFloat() && !isa<ComplexType>(resEltType))
return {};
// Constant attributes might have a different type than the return type.
// Convert them before creating the dense elements attribute.
auto convertedElements = llvm::map_to_vector(elements, [&](Attribute attr) {
- return convertNumericAttr(attr, destEltType);
+ return convertNumericAttr(attr, resEltType);
});
- return DenseElementsAttr::get(destVecType, convertedElements);
+ return DenseElementsAttr::get(resVecType, convertedElements);
}
OpFoldResult FromElementsOp::fold(FoldAdaptor adaptor) {
@@ -4027,7 +4027,7 @@ static Value foldInsertUseChain(InsertOp insertOp) {
return {};
insertOp.setOperand(1, destInsert.getDest());
- return insertOp.getResult();
+ return insertOp.getDest();
}
void InsertOp::getCanonicalizationPatterns(RewritePatternSet &results,
@@ -7646,7 +7646,7 @@ class FoldTransposeFromElements final : public OpRewritePattern<TransposeOp> {
if (!fromElementsOp)
return failure();
- VectorType srcTy = fromElementsOp.getDest().getType();
+ VectorType srcTy = fromElementsOp.getResult().getType();
VectorType dstTy = transposeOp.getType();
ArrayRef<int64_t> permutation = transposeOp.getPermutation();
diff --git a/mlir/lib/Dialect/Vector/Transforms/LowerVectorInterleave.cpp b/mlir/lib/Dialect/Vector/Transforms/LowerVectorInterleave.cpp
index 8f81dbb6363255..f797d9417c1fcd 100644
--- a/mlir/lib/Dialect/Vector/Transforms/LowerVectorInterleave.cpp
+++ b/mlir/lib/Dialect/Vector/Transforms/LowerVectorInterleave.cpp
@@ -137,9 +137,9 @@ class UnrollDeinterleaveOp final
auto deinterleave =
vector::DeinterleaveOp::create(rewriter, loc, extractSrc);
evenResult = vector::InsertOp::create(
- rewriter, loc, deinterleave.getRes1(), evenResult, position);
+ rewriter, loc, deinterleave.getResultEven(), evenResult, position);
oddResult = vector::InsertOp::create(
- rewriter, loc, deinterleave.getRes2(), oddResult, position);
+ rewriter, loc, deinterleave.getResultOdd(), oddResult, position);
}
rewriter.replaceOp(op, ValueRange{evenResult, oddResult});
return success();
diff --git a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
index e237ae0568ae43..b86620c4efdf91 100644
--- a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
+++ b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
@@ -1959,14 +1959,14 @@ static Value rewriteI8ToI4Trunc(PatternRewriter &rewriter, Location loc,
Value zeroOutMask = arith::ConstantOp::create(
rewriter, loc, DenseElementsAttr::get(deinterI8VecType, i8LowBitMask));
Value zeroOutLow = arith::AndIOp::create(
- rewriter, loc, deinterleaveOp.getRes1(), zeroOutMask);
+ rewriter, loc, deinterleaveOp.getResultEven(), zeroOutMask);
// 3. Move high i4 values to upper side of the byte.
constexpr int8_t bitsToShift = 4;
auto shiftValues = arith::ConstantOp::create(
rewriter, loc, DenseElementsAttr::get(deinterI8VecType, bitsToShift));
- Value shlHigh = arith::ShLIOp::create(rewriter, loc, deinterleaveOp.getRes2(),
- shiftValues);
+ Value shlHigh = arith::ShLIOp::create(
+ rewriter, loc, deinterleaveOp.getResultOdd(), shiftValues);
// 4. Merge high and low i4 values.
auto mergedHiLowOp = arith::OrIOp::create(rewriter, loc, zeroOutLow, shlHigh);
diff --git a/mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp b/mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
index 19abe44081eb43..b7fdc9ff5186d9 100644
--- a/mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
+++ b/mlir/lib/Dialect/Vector/Transforms/VectorUnroll.cpp
@@ -1714,10 +1714,10 @@ struct UnrollDeinterleavePattern
vector::DeinterleaveOp::create(rewriter, loc, sourceSlice);
resultOdd = rewriter.createOrFold<vector::InsertStridedSliceOp>(
- loc, deinterleaveSlice.getRes1(), resultOdd, resultOffsets,
+ loc, deinterleaveSlice.getResultEven(), resultOdd, resultOffsets,
resultStrides);
resultEven = rewriter.createOrFold<vector::InsertStridedSliceOp>(
- loc, deinterleaveSlice.getRes2(), resultEven, resultOffsets,
+ loc, deinterleaveSlice.getResultOdd(), resultEven, resultOffsets,
resultStrides);
}
diff --git a/mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToLaneDistribute.cpp b/mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToLaneDistribute.cpp
index 4f9a37851665ca..3a12b589b45f3e 100644
--- a/mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToLaneDistribute.cpp
+++ b/mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToLaneDistribute.cpp
@@ -2524,8 +2524,8 @@ struct SgToLaneConvertLayoutDeinterleaveSelect
Value isFirstGroup = arith::CmpIOp::create(
rewriter, loc, arith::CmpIPredicate::eq, group, zero);
Value selected = arith::SelectOp::create(rewriter, loc, isFirstGroup,
- deinterleaved.getRes1(),
- deinterleaved.getRes2());
+ deinterleaved.getResultEven(),
+ deinterleaved.getResultOdd());
rewriter.replaceOpWithNewOp<vector::ShapeCastOp>(
op, redistribution->distributedTarget, selected);
return success();
diff --git a/mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp b/mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
index 9e2a0401900e08..0ce267774ba54d 100644
--- a/mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
+++ b/mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
@@ -1465,8 +1465,8 @@ struct WgToSgVectorDeinterleaveOp
for (auto src : adaptor.getSource()) {
auto newDeinterleave =
vector::DeinterleaveOp::create(rewriter, op.getLoc(), src);
- newRes1Ops.push_back(newDeinterleave.getRes1());
- newRes2Ops.push_back(newDeinterleave.getRes2());
+ newRes1Ops.push_back(newDeinterleave.getResultEven());
+ newRes2Ops.push_back(newDeinterleave.getResultOdd());
}
SmallVector<SmallVector<Value>> results = {newRes1Ops, newRes2Ops};
diff --git a/mlir/test/Dialect/Vector/CPU/ArmSVE/vector-bfmmla.mlir b/mlir/test/Dialect/Vector/CPU/ArmSVE/vector-bfmmla.mlir
index ca9d91576b5126..99273c02d14cbb 100644
--- a/mlir/test/Dialect/Vector/CPU/ArmSVE/vector-bfmmla.mlir
+++ b/mlir/test/Dialect/Vector/CPU/ArmSVE/vector-bfmmla.mlir
@@ -67,9 +67,9 @@
// CHECK-NEXT: %[[T36:.+]] = vector.scalable.insert %[[PACK_RES_00]], %[[T0]][0] : vector<[4]xf32> into vector<[8]xf32>
// CHECK-NEXT: %[[T37:.+]] = vector.scalable.insert %[[PACK_RES_01]], %[[T36]][4] : vector<[4]xf32> into vector<[8]xf32>
// CHECK-NEXT: %[[T38:.+]] = vector.bitcast %[[T37]] : vector<[8]xf32> to vector<[4]xi64>
-// CHECK-NEXT: %res1, %res2 = vector.deinterleave %[[T38]] : vector<[4]xi64> -> vector<[2]xi64>
-// CHECK-NEXT: %[[UNPACK_RES_00:.+]] = vector.bitcast %res1 : vector<[2]xi64> to vector<[4]xf32>
-// CHECK-NEXT: %[[UNPACK_RES_01:.+]] = vector.bitcast %res2 : vector<[2]xi64> to vector<[4]xf32>
+// CHECK-NEXT: %resultEven, %resultOdd = vector.deinterleave %[[T38]] : vector<[4]xi64> -> vector<[2]xi64>
+// CHECK-NEXT: %[[UNPACK_RES_00:.+]] = vector.bitcast %resultEven : vector<[2]xi64> to vector<[4]xf32>
+// CHECK-NEXT: %[[UNPACK_RES_01:.+]] = vector.bitcast %resultOdd : vector<[2]xi64> to vector<[4]xf32>
// CHECK-NEXT: %[[TMP_OUT_0:.+]] = vector.insert %[[UNPACK_RES_00]], %[[UB]] [0] : vector<[4]xf32> into vector<4x[4]xf32>
// CHECK-NEXT: %[[TMP_OUT_1:.+]] = vector.insert %[[UNPACK_RES_01]], %[[TMP_OUT_0]] [1] : vector<[4]xf32> into vector<4x[4]xf32>
@@ -77,9 +77,9 @@
// CHECK-NEXT: %[[T43:.+]] = vector.scalable.insert %[[PACK_RES_10]], %[[T0]][0] : vector<[4]xf32> into vector<[8]xf32>
// CHECK-NEXT: %[[T44:.+]] = vector.scalable.insert %[[PACK_RES_11]], %[[T43]][4] : vector<[4]xf32> into vector<[8]xf32>
// CHECK-NEXT: %[[T45:.+]] = vector.bitcast %[[T44]] : vector<[8]xf32> to vector<[4]xi64>
-// CHECK-NEXT: %res1_0, %res2_1 = vector.deinterleave %[[T45]] : vector<[4]xi64> -> vector<[2]xi64>
-// CHECK-NEXT: %[[UNPACK_RES_10:.+]] = vector.bitcast %res1_0 : vector<[2]xi64> to vector<[4]xf32>
-// CHECK-NEXT: %[[UNPACK_RES_11:.+]] = vector.bitcast %res2_1 : vector<[2]xi64> to vector<[4]xf32>
+// CHECK-NEXT: %resultEven_0, %resultOdd_1 = vector.deinterleave %[[T45]] : vector<[4]xi64> -> vector<[2]xi64>
+// CHECK-NEXT: %[[UNPACK_RES_10:.+]] = vector.bitcast %resultEven_0 : vector<[2]xi64> to vector<[4]xf32>
+// CHECK-NEXT: %[[UNPACK_RES_11:.+]] = vector.bitcast %resultOdd_1 : vector<[2]xi64> to vector<[4]xf32>
// CHECK-NEXT: %[[TMP_OUT_2:.+]] = vector.insert %[[UNPACK_RES_10]], %[[TMP_OUT_1]] [2] : vector<[4]xf32> into vector<4x[4]xf32>
// CHECK-NEXT: %[[OUT:.+]] = vector.insert %[[UNPACK_RES_11]], %[[TMP_OUT_2]] [3] : vector<[4]xf32> into vector<4x[4]xf32>
// CHECK-NEXT: return %[[OUT]] : vector<4x[4]xf32>
diff --git a/mlir/test/Dialect/Vector/CPU/ArmSVE/vector-smmla.mlir b/mlir/test/Dialect/Vector/CPU/ArmSVE/vector-smmla.mlir
index 404ef87380c9c5..e91faeef576e05 100644
--- a/mlir/test/Dialect/Vector/CPU/ArmSVE/vector-smmla.mlir
+++ b/mlir/test/Dialect/Vector/CPU/ArmSVE/vector-smmla.mlir
@@ -71,9 +71,9 @@
// CHECK-NEXT: %[[T36:[0-9]+]] = vector.scalable.insert %[[PACK_RES_00]], %[[P0]][0] : vector<[4]xi32> into vector<[8]xi32>
// CHECK-NEXT: %[[T37:[0-9]+]] = vector.scalable.insert %[[PACK_RES_01]], %[[T36]][4] : vector<[4]xi32> into vector<[8]xi32>
// CHECK-NEXT: %[[T38:[0-9]+]] = vector.bitcast %[[T37]] : vector<[8]xi32> to vector<[4]xi64>
-// CHECK-NEXT: %res1, %res2 = vector.deinterleave %[[T38]] : vector<[4]xi64> -> vector<[2]xi64>
-// CHECK-NEXT: %[[UNPACK_RES_0:[0-9]+]] = vector.bitcast %res1 : vector<[2]xi64> to vector<[4]xi32>
-// CHECK-NEXT: %[[UNPACK_RES_1:[0-9]+]] = vector.bitcast %res2 : vector<[2]xi64> to vector<[4]xi32>
+// CHECK-NEXT: %resultEven, %resultOdd = vector.deinterleave %[[T38]] : vector<[4]xi64> -> vector<[2]xi64>
+// CHECK-NEXT: %[[UNPACK_RES_0:[0-9]+]] = vector.bitcast %resultEven : vector<[2]xi64> to vector<[4]xi32>
+// CHECK-NEXT: %[[UNPACK_RES_1:[0-9]+]] = vector.bitcast %resultOdd : vector<[2]xi64> to vector<[4]xi32>
// CHECK-NEXT: %[[TMP_OUT_0:[0-9]+]] = vector.insert %[[UNPACK_RES_0]], %[[P1]] [0] : vector<[4]xi32> into vector<4x[4]xi32>
// CHECK-NEXT: %[[TMP_OUT_1:[0-9]+]] = vector.insert %[[UNPACK_RES_1]], %[[TMP_OUT_0]] [1] : vector<[4]xi32> into vector<4x[4]xi32>
@@ -81,9 +81,9 @@
// CHECK-NEXT: %[[T43:[0-9]+]] = vector.scalable.insert %[[PACK_RES_10]], %[[P0]][0] : vector<[4]xi32> into vector<[8]xi32>
// CHECK-NEXT: %[[T44:[0-9]+]] = vector.scalable.insert %[[PACK_RES_11]], %[[T43]][4] : vector<[4]xi32> into vector<[8]xi32>
// CHECK-NEXT: %[[T45:[0-9]+]] = vector.bitcast %[[T44]] : vector<[8]xi32> to vector<[4]xi64>
-// CHECK-NEXT: %res1_0, %res2_1 = vector.deinterleave %[[T45]] : vector<[4]xi64> -> vector<[2]xi64>
-// CHECK-NEXT: %[[UNPACK_RES_2:[0-9]+]] = vector.bitcast %res1_0 : vector<[2]xi64> to vector<[4]xi32>
-// CHECK-NEXT: %[[UNPACK_RES_3:[0-9]+]] = vector.bitcast %res2_1 : vector<[2]xi64> to vector<[4]xi32>
+// CHECK-NEXT: %resultEven_0, %resultOdd_1 = vector.deinterleave %[[T45]] : vector<[4]xi64> -> vector<[2]xi64>
+// CHECK-NEXT: %[[UNPACK_RES_2:[0-9]+]] = vector.bitcast %resultEven_0 : vector<[2]xi64> to vector<[4]xi32>
+// CHECK-NEXT: %[[UNPACK_RES_3:[0-9]+]] = vector.bitcast %resultOdd_1 : vector<[2]xi64> to vector<[4]xi32>
// CHECK-NEXT: %[[TMP_OUT_2:[0-9]+]] = vector.insert %[[UNPACK_RES_2]], %[[TMP_OUT_1]] [2] : vector<[4]xi32> into vector<4x[4]xi32>
// CHECK-NEXT: %[[OUT:[0-9]+]] = vector.insert %[[UNPACK_RES_3]], %[[TMP_OUT_2]] [3] : vector<[4]xi32> into vector<4x[4]xi32>
@@ -161,9 +161,9 @@ func.func @test_vector_contract_to_smmla(%lhs: vector<4x8xi8>,
// CHECK-NEXT: %[[T36:[0-9]+]] = vector.scalable.insert %[[PACK_RES_00]], %[[P0]][0] : vector<[4]xi32> into vector<[8]xi32>
// CHECK-NEXT: %[[T37:[0-9]+]] = vector.scalable.insert %[[PACK_RES_01]], %[[T36]][4] : vector<[4]xi32> into vector<[8]xi32>
// CHECK-NEXT: %[[T38:[0-9]+]] = vector.bitcast %[[T37]] : vector<[8]xi32> to vector<[4]xi64>
-// CHECK-NEXT: %res1, %res2 = vector.deinterleave %[[T38]] : vector<[4]xi64> -> vector<[2]xi64>
-// CHECK-NEXT: %[[UNPACK_RES_0:[0-9]+]] = vector.bitcast %res1 : vector<[2]xi64> to vector<[4]xi32>
-// CHECK-NEXT: %[[UNPACK_RES_1:[0-9]+]] = vector.bitcast %res2 : vector<[2]xi64> to vector<[4]xi32>
+// CHECK-NEXT: %resultEven, %resultOdd = vector.deinterleave %[[T38]] : vector<[4]xi64> -> vector<[2]xi64>
+// CHECK-NEXT: %[[UNPACK_RES_0:[0-9]+]] = vector.bitcast %resultEven : vector<[2]xi64> to vector<[4]xi32>
+// CHECK-NEXT: %[[UNPACK_RES_1:[0-9]+]] = vector.bitcast %resultOdd : vector<[2]xi64> to vector<[4]xi32>
// CHECK-NEXT: %[[TMP_OUT_0:[0-9]+]] = vector.insert %[[UNPACK_RES_0]], %[[P1]] [0] : vector<[4]xi32> into vector<4x[4]xi32>
// CHECK-NEXT: %[[TMP_OUT_1:[0-9]+]] = vector.insert %[[UNPACK_RES_1]], %[[TMP_OUT_0]] [1] : vector<[4]xi32> into vector<4x[4]xi32>
@@ -171,9 +171,9 @@ func.func @test_vector_contract_to_smmla(%lhs: vector<4x8xi8>,
// CHECK-NEXT: %[[T43:[0-9...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/238070
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