[Mlir-commits] [mlir] [MLIR][Affine] Add MDG edges between accesses to aliasing memref views (PR #237726)

[Sajid Zubair]

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Sajid-Zubair wrote:

Thanks, done. I now precompute, per view, the list of accessing nodes together with whether each may write/free that view, so the memrefAccesses/getNode lookups and the hasStore/hasFree scans happen once per (node, view) instead of inside the pair loops. I also skip bases with a single memref value up front, so functions without views don’t pay for building that table.

https://github.com/llvm/llvm-project/pull/237726