[Mlir-commits] [mlir] [MLIR][XeGPUToXeVM] Add vector-shuffle for interleaved row-values (PR #233509)

[Dmitry Chigarev]

dchigarev wrote:

> if I understand correctly the interleaved format is the expected format here

@charithaintc I'm not sure it's expected here: the whole xegpu->xevm infra expects the loaded lane vector to be row-major, and it **is** row-major in all cases except this particular one, where each lane gets multiple rows of a transposed load and receives them as a col-major tile (coincidentally, it's also the only case that was untested before).

So the issue is that all the xegpu/xevm code that consumes the loaded `<16xi32>` vector (i.e. the `extract_strided_slice` splits inserted by sg-to-lane) expects it to be row-major, while in this particular case it is loaded as col-major. A shuffle seems to be the simplest way to fix this, though I'm not 100% sure it's the <i>proper</i> one. Maybe this col-major behavior could theoretically be expressed via `xegpu.layout` somehow, so that `sg-to-lane` could generate code that respects the loaded vector's layout (row/col-major), but I'm not sure the xegpu level should know how exactly the hardware places the loaded data into registers, so the xevm level seemed like the most suitable place to fix it (keep the contract that all the consumers of `xegpu.load_nd` get row-major vectors).

cc @Jianhui-Li 

https://github.com/llvm/llvm-project/pull/233509