[Mlir-commits] [mlir] [MLIR][NVGPU] Add convert.fpext and convert.fptrunc Ops (PR #199700)

[Durgadoss R]

================
@@ -671,4 +671,80 @@ def NVGPU_RcpOp : NVGPU_Op<"rcp", [Pure,
   let hasVerifier = 1;
 }
 
+//===----------------------------------------------------------------------===//
+// NVGPU Conversion Ops
+//===----------------------------------------------------------------------===//
+
+def Int8OrFloatLike : TypeConstraint<
+    Or<[FloatLike.predicate,
+        I8.predicate,
+        ValueSemanticsContainerOf<[I8]>.predicate]>,
+    "scalar, vector, or tensor of i8 or floats">;
+def AnyI32Like : TypeOrValueSemanticsContainer<I32, "scalar i32 or vector of i32">;
+
+def NVGPU_FPTruncOp : NVGPU_Op<"convert.fptrunc",
+    [Pure]> {
+  let summary = "Truncate floating-point to narrower floating-point";
+  let description = [{
+    Truncate a floating-point value to a smaller floating-point type.
+    Destination must be strictly narrower than source.
+
+    Supported paths: f32->f16, f32->bf16, f32->f8, f32->f6, f32->f4,
+    f16->f8, f16->f4, bf16->f8, bf16->f4.
----------------
durga4github wrote:

can we rewrite this as a grouping of source so that it is easy to know that we support 3-src formats now?
```
f32->{f16, bf16, f8, f6, f4}
f16->{f8, f4}
bf16->{f8, f4}
```

and with that I wonder the missing f6 types for f16/bf16 src types is because we dont have NVVM Dialect conversions yet? (i.e. ISA itself does not support + no intrinsics yet etc.)

https://github.com/llvm/llvm-project/pull/199700