[Mlir-commits] [mlir] [mlir][vector] Add fold to transfer_{read, write} vector<1xT> (PR #196598)

[Erick Ochoa Lopez]

amd-eochoalo wrote:

There is a negative test for the case of vector<4xT> (which this pattern won't match). See in vector-transfer-to-vector-load-store.mlir

```
// TODO: transfer_read/write cannot be lowered to vector.load/store yet when the
// permutation map is not the minor identity map (up to broadcasting).
// CHECK-LABEL:   func @transfer_perm_map(
// CHECK-SAME:      %[[MEM:.*]]: memref<8x8xf32>,
// CHECK-SAME:      %[[IDX:.*]]: index) -> vector<4xf32> {
// CHECK-NEXT:      %[[CF0:.*]] = arith.constant 0.000000e+00 : f32
// CHECK-NEXT:      %[[RES:.*]] = vector.transfer_read %[[MEM]][%[[IDX]], %[[IDX]]], %[[CF0]] {in_bounds = [true], permutation_map = #{{.*}}} : memref<8x8xf32>, vector<4xf32>
// CHECK-NEXT:      return %[[RES]] : vector<4xf32>
// CHECK-NEXT:    }

func.func @transfer_perm_map(%mem : memref<8x8xf32>, %idx : index) -> vector<4xf32> {
  %cf0 = arith.constant 0.0 : f32
  %res = vector.transfer_read %mem[%idx, %idx], %cf0 {in_bounds = [true], permutation_map = affine_map<(d0, d1) -> (d0)>} : memref<8x8xf32>, vector<4xf32>
  return %res : vector<4xf32>
}
```

https://github.com/llvm/llvm-project/pull/196598