[Mlir-commits] [mlir] [MLIR][GPU] Add gpu-lower-to-rocdl-pipeline meta-pass (PR #196751)

[Fabian Mora]

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@@ -64,6 +64,58 @@ struct GPUToNVVMPipelineOptions
       llvm::cl::init(true)};
 };
 
+/// Options for the gpu to rocdl pipeline.
+struct GPUToROCDLPipelineOptions
+    : public PassPipelineOptions<GPUToROCDLPipelineOptions> {
+  PassOptions::Option<int64_t> indexBitWidth{
+      *this, "index-bitwidth",
+      llvm::cl::desc("Bitwidth of the index type for the host (warning this "
+                     "should be 64 until the GPU layering is fixed)"),
+      llvm::cl::init(64)};
+  PassOptions::Option<std::string> hsacoTriple{
+      *this, "hsaco-triple",
+      llvm::cl::desc("Triple to use to serialize to hsaco."),
+      llvm::cl::init("amdgcn-amd-amdhsa")};
+  PassOptions::Option<std::string> hsacoChip{
+      *this, "hsaco-chip", llvm::cl::desc("Chip to use to serialize to hsaco."),
+      llvm::cl::init("gfx900")};
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fabianmcg wrote:

I know the target attr uses this as default, but I'm not sure it makes to have it. In the NVVM pipeline makes sense because ptx, but I think this is a footgun for new users to AMDGPUs, so I'd propose to remove it.

https://github.com/llvm/llvm-project/pull/196751