[Mlir-commits] [mlir] dc93944 - [mlir][AMDGPU] Add, unify verification of memref index counts (#196657)
llvmlistbot at llvm.org
llvmlistbot at llvm.org
Fri May 8 15:50:59 PDT 2026
Author: Krzysztof Drewniak
Date: 2026-05-08T15:50:55-07:00
New Revision: dc93944caaa93648a89e72021602556ce39003ee
URL: https://github.com/llvm/llvm-project/commit/dc93944caaa93648a89e72021602556ce39003ee
DIFF: https://github.com/llvm/llvm-project/commit/dc93944caaa93648a89e72021602556ce39003ee.diff
LOG: [mlir][AMDGPU] Add, unify verification of memref index counts (#196657)
This PR verifies that, on operations that have
`%memref[%idx0, %idx1, ...]` arguments, the number of indices matches
the rank of the memref being passed in.
While we're here, fixes capitalization for certain verification error
messages.
Assisted-by: Codex 5.5 (handled much of the implementation)
Added:
Modified:
mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td
mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp
mlir/test/Dialect/AMDGPU/invalid.mlir
Removed:
################################################################################
diff --git a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td
index cea6c7c76fdc4..0ec788e21f0bf 100644
--- a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td
+++ b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td
@@ -1637,9 +1637,6 @@ class AMDGPU_DmaBaseOp<string mnemonic, Type outType> :
Variadic<Index>:$lds_indices)>,
Results<(outs outType: $base)> {
- // TODO:
- // * Add verifiers to make sure that the number of indices do not exceed the number of dimensions.
-
let assemblyFormat = [{
$global `[` $global_indices `]` `,` $lds `[` $lds_indices `]` attr-dict `:` type($global) `,` type($lds) `->` type(results)
}];
diff --git a/mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp b/mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp
index 03be67f33a1df..fd9a153ada2b8 100644
--- a/mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp
+++ b/mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp
@@ -38,6 +38,19 @@
using namespace mlir;
using namespace mlir::amdgpu;
+/// Verifies that the number of indices matches the rank of the indexed memref,
+/// emitting an op error mentioning `indexName` on mismatch.
+template <typename OpTy>
+static LogicalResult verifyIndexCount(OpTy op, StringRef indexName,
+ MemRefType memrefType,
+ int64_t numIndices) {
+ int64_t rank = memrefType.getRank();
+ if (rank != numIndices)
+ return op.emitOpError("expected ")
+ << rank << " " << indexName << " indices, got " << numIndices;
+ return success();
+}
+
//===----------------------------------------------------------------------===//
// 8-bit float ops
//===----------------------------------------------------------------------===//
@@ -177,14 +190,11 @@ static LogicalResult verifyRawBufferOp(T &op) {
if (!isGlobal)
return op.emitOpError(
- "Buffer ops must operate on a memref in global memory");
+ "buffer ops must operate on a memref in global memory");
if (!bufferType.hasRank())
return op.emitOpError(
- "Cannot meaningfully buffer_store to an unranked memref");
- if (static_cast<int64_t>(op.getIndices().size()) != bufferType.getRank())
- return op.emitOpError("Expected " + Twine(bufferType.getRank()) +
- " indices to memref");
- return success();
+ "cannot meaningfully buffer_store to an unranked memref");
+ return verifyIndexCount(op, "buffer", bufferType, op.getIndices().size());
}
LogicalResult RawBufferLoadOp::verify() { return verifyRawBufferOp(*this); }
@@ -948,6 +958,12 @@ LogicalResult GatherToLDSOp::verify() {
MemRefType srcType = cast<MemRefType>(getSrc().getType());
MemRefType dstType = cast<MemRefType>(getDst().getType());
+ if (failed(
+ verifyIndexCount(*this, "source", srcType, getSrcIndices().size())) ||
+ failed(verifyIndexCount(*this, "destination", dstType,
+ getDstIndices().size())))
+ return failure();
+
if (dstType.getRank() > 0 && !dstType.areTrailingDimsContiguous(1))
return emitOpError("destination type inner most dim must be contiguous");
@@ -1020,6 +1036,12 @@ LogicalResult GlobalLoadAsyncToLDSOp::verify() {
MemRefType srcType = cast<MemRefType>(getSrc().getType());
MemRefType dstType = cast<MemRefType>(getDst().getType());
+ if (failed(
+ verifyIndexCount(*this, "source", srcType, getSrcIndices().size())) ||
+ failed(verifyIndexCount(*this, "destination", dstType,
+ getDstIndices().size())))
+ return failure();
+
if (srcType.getElementType() != dstType.getElementType())
return emitOpError("source and destination element types must match");
@@ -1050,6 +1072,10 @@ LogicalResult GlobalLoadAsyncToLDSOp::verify() {
LogicalResult TransposeLoadOp::verify() {
MemRefType srcType = cast<MemRefType>(getSrc().getType());
+ if (failed(
+ verifyIndexCount(*this, "source", srcType, getSrcIndices().size())))
+ return failure();
+
if (!hasWorkgroupMemorySpace(srcType.getMemorySpace()))
return emitOpError("source memory address space must be Workgroup");
@@ -1086,6 +1112,10 @@ LogicalResult TransposeLoadOp::verify() {
LogicalResult GlobalTransposeLoadOp::verify() {
MemRefType srcType = cast<MemRefType>(getSrc().getType());
+ if (failed(
+ verifyIndexCount(*this, "source", srcType, getSrcIndices().size())))
+ return failure();
+
if (!hasGlobalMemorySpace(srcType.getMemorySpace()))
return emitOpError("source memory address space must be Global");
@@ -1124,6 +1154,11 @@ template <typename BaseOp>
static LogicalResult verifyBase(BaseOp op) {
auto ldsType = cast<MemRefType>(op.getLds().getType());
auto globalType = cast<MemRefType>(op.getGlobal().getType());
+ if (failed(verifyIndexCount(op, "global", globalType,
+ op.getGlobalIndices().size())) ||
+ failed(verifyIndexCount(op, "lds", ldsType, op.getLdsIndices().size())))
+ return failure();
+
if (!hasWorkgroupMemorySpace(ldsType.getMemorySpace()))
return op.emitOpError(
"lds memref must have workgroup address space attribute.");
@@ -1196,9 +1231,17 @@ static LogicalResult verifyDescriptorOp(DescriptorOp op) {
"element type width must be 1, 2, 4 or 8 bytes, but was ")
<< elementTypeWidth << " bits long";
+ if (!op.getAtomicBarrierAddress() && !op.getAtomicBarrierIndices().empty())
+ return op.emitOpError(
+ "atomic barrier indices require an atomic barrier address");
+
if (Value atomicBarrierAddress = op.getAtomicBarrierAddress()) {
auto atomicBarrierAddressType =
cast<MemRefType>(atomicBarrierAddress.getType());
+ if (failed(verifyIndexCount(op, "atomic barrier", atomicBarrierAddressType,
+ op.getAtomicBarrierIndices().size())))
+ return failure();
+
bool barrierInLDS =
hasWorkgroupMemorySpace(atomicBarrierAddressType.getMemorySpace());
if (!barrierInLDS)
@@ -1417,6 +1460,10 @@ void ScaledMFMAOp::getCanonicalizationPatterns(RewritePatternSet &results,
template <typename T>
static LogicalResult verifyDsBarrierOpCommon(T &op) {
MemRefType memrefType = llvm::cast<MemRefType>(op.getBase().getType());
+ if (failed(
+ verifyIndexCount(op, "barrier", memrefType, op.getIndices().size())))
+ return failure();
+
if (!hasWorkgroupMemorySpace(memrefType.getMemorySpace()))
return op.emitOpError("barrier must be in workgroup (LDS) memory");
@@ -1446,18 +1493,15 @@ LogicalResult DsBarrierArriveOp::verify() {
LogicalResult GlobalPrefetchOp::verify() {
auto src = cast<MemRefType>(getSrc().getType());
+ if (failed(verifyIndexCount(*this, "source", src, getIndices().size())))
+ return failure();
+
Attribute memSpace = src.getMemorySpace();
if (!memSpace)
return this->emitOpError("the source must have address space attribute");
if (!hasGlobalMemorySpace(memSpace))
return this->emitOpError("the source must reside in global address space");
- ArrayRef<int64_t> srcShape = src.getShape();
- const size_t numIndices = getIndices().size();
- if (srcShape.size() != numIndices)
- return this->emitOpError(
- "the number of indices must match the source shape size");
-
const LoadTemporalHint temporalHint = getTemporalHint();
const Scope scope = getCacheScope();
const bool isSpeculative = getSpeculative();
diff --git a/mlir/test/Dialect/AMDGPU/invalid.mlir b/mlir/test/Dialect/AMDGPU/invalid.mlir
index 4fe3185a27bd1..4e4cfe53298c7 100644
--- a/mlir/test/Dialect/AMDGPU/invalid.mlir
+++ b/mlir/test/Dialect/AMDGPU/invalid.mlir
@@ -245,6 +245,14 @@ func.func @fat_raw_buffer_cast_stripping_offset_affine_map(%m: memref<8xi32, aff
// -----
+func.func @raw_buffer_load_wrong_num_indices(%src: memref<4x4xf32>, %idx: i32) -> f32 {
+ // expected-error at +1 {{'amdgpu.raw_buffer_load' op expected 2 buffer indices, got 1}}
+ %0 = amdgpu.raw_buffer_load %src[%idx] : memref<4x4xf32>, i32 -> f32
+ func.return %0 : f32
+}
+
+// -----
+
func.func @swizzle_invalid_type(%arg0 : si32) -> si32 {
// expected-error at +1 {{'amdgpu.swizzle_bitmode' op operand #0 must be Integer or Float or fixed-length vector of Integer or Float values of ranks 1}}
%0 = amdgpu.swizzle_bitmode %arg0 1 2 4 : si32
@@ -317,6 +325,14 @@ func.func @transpose_load_vector_size_i8(%idx1 : index, %idx2 : index, %mem : me
// -----
+func.func @transpose_load_wrong_num_indices(%idx : index, %mem : memref<128x32xf16, #gpu.address_space<workgroup>>) -> vector<4xf16> {
+ // expected-error at +1 {{'amdgpu.transpose_load' op expected 2 source indices, got 1}}
+ %0 = amdgpu.transpose_load %mem[%idx] : memref<128x32xf16, #gpu.address_space<workgroup>> -> vector<4xf16>
+ func.return %0 : vector<4xf16>
+}
+
+// -----
+
func.func @global_transpose_load_wrong_addrspace(%i : index, %j : index,
%src : memref<128x256xf16, 3>) -> vector<8xf16> {
// expected-error at +1 {{'amdgpu.global_transpose_load' op source memory address space must be Global}}
@@ -327,6 +343,14 @@ func.func @global_transpose_load_wrong_addrspace(%i : index, %j : index,
// -----
+func.func @global_transpose_load_wrong_num_indices(%idx : index, %mem : memref<128x32xf16, #gpu.address_space<global>>) -> vector<8xf16> {
+ // expected-error at +1 {{'amdgpu.global_transpose_load' op expected 2 source indices, got 1}}
+ %0 = amdgpu.global_transpose_load %mem[%idx] : memref<128x32xf16, #gpu.address_space<global>> -> vector<8xf16>
+ func.return %0 : vector<8xf16>
+}
+
+// -----
+
func.func @gather_to_lds_non_lds(%idx1 : index, %mem1 : memref<32xf16>, %mem2 : memref<32xf16>) {
// expected-error at +1 {{'amdgpu.gather_to_lds' op destination memory address space must be Workgroup}}
amdgpu.gather_to_lds %mem1[%idx1], %mem2[%idx1] : vector<2xf16>, memref<32xf16>, memref<32xf16>
@@ -343,6 +367,16 @@ func.func @gather_to_lds_non_lds(%idx1 : index, %mem1 : memref<32xf16>, %mem2 :
// -----
+func.func @gather_to_lds_wrong_num_indices(%idx : index,
+ %src : memref<32x32xf16, #gpu.address_space<global>>,
+ %dst : memref<32x32xf16, #gpu.address_space<workgroup>>) {
+ // expected-error at +1 {{'amdgpu.gather_to_lds' op expected 2 source indices, got 1}}
+ amdgpu.gather_to_lds %src[%idx], %dst[%idx, %idx] : vector<2xf16>, memref<32x32xf16, #gpu.address_space<global>>, memref<32x32xf16, #gpu.address_space<workgroup>>
+ func.return
+}
+
+// -----
+
func.func @global_load_async_to_lds_non_lds(%idx1 : index,
%mem1 : memref<32xf32, #gpu.address_space<global>>,
%mem2 : memref<32xf32>) {
@@ -378,6 +412,18 @@ func.func @global_load_async_to_lds_src_not_global(%idx1 : index,
// -----
+func.func @global_load_async_to_lds_wrong_num_indices(%idx : index,
+ %src : memref<32x32xf32, #gpu.address_space<global>>,
+ %dst : memref<32x32xf32, #gpu.address_space<workgroup>>) {
+ // expected-error at +1 {{'amdgpu.global_load_async_to_lds' op expected 2 destination indices, got 1}}
+ amdgpu.global_load_async_to_lds %src[%idx, %idx], %dst[%idx]
+ : f32, memref<32x32xf32, #gpu.address_space<global>>,
+ memref<32x32xf32, #gpu.address_space<workgroup>>
+ func.return
+}
+
+// -----
+
func.func @scaled_mfma_invalid_m(%arg0 : vector<4xf8E8M0FNU>, %arg1 : vector<32xf4E2M1FN>, %arg2 : vector<16xf32>) -> vector<16xf32> {
// expected-error at +1 {{'amdgpu.scaled_mfma' op attribute 'm' failed to satisfy constraint: 32-bit signless integer attribute whose value is one of {16, 32}}}
%0 = amdgpu.scaled_mfma 8x32x64 (%arg0[0] * %arg1) * (%arg0[1] * %arg1) + %arg2 : vector<4xf8E8M0FNU>, vector<32xf4E2M1FN>, vector<4xf8E8M0FNU>, vector<32xf4E2M1FN>, vector<16xf32>
@@ -441,6 +487,26 @@ func.func @make_gather_dma_base_invalid_addressspace(%idx: index, %smem : memref
// -----
+func.func @make_dma_base_wrong_num_indices(%idx: index,
+ %global: memref<8x8xi32, #gpu.address_space<global>>,
+ %lds: memref<8x8xi32, #gpu.address_space<workgroup>>) {
+ // expected-error at +1 {{'amdgpu.make_dma_base' op expected 2 global indices, got 1}}
+ amdgpu.make_dma_base %global[%idx], %lds[%idx, %idx] : memref<8x8xi32, #gpu.address_space<global>>, memref<8x8xi32, #gpu.address_space<workgroup>> -> !amdgpu.tdm_base<i32>
+ return
+}
+
+// -----
+
+func.func @make_gather_dma_base_wrong_num_indices(%idx: index,
+ %global: memref<8x8xi32, #gpu.address_space<global>>,
+ %lds: memref<8x8xi32, #gpu.address_space<workgroup>>) {
+ // expected-error at +1 {{'amdgpu.make_gather_dma_base' op expected 2 lds indices, got 1}}
+ amdgpu.make_gather_dma_base %global[%idx, %idx], %lds[%idx] : memref<8x8xi32, #gpu.address_space<global>>, memref<8x8xi32, #gpu.address_space<workgroup>> -> !amdgpu.tdm_gather_base<i32, i16>
+ return
+}
+
+// -----
+
func.func @make_dma_base_invalid_barrier(%base: !amdgpu.tdm_base<i32>, %barrier: memref<8x!amdgpu.ds_barrier_state>, %idx: index) {
// expected-error at +1 {{'amdgpu.make_dma_descriptor' op atomic barrier address must be in LDS.}}
amdgpu.make_dma_descriptor %base globalSize [64, 64] globalStride [64, 1] sharedSize [64, 64] atomicBarrier(%barrier[%idx] : memref<8x!amdgpu.ds_barrier_state>) : !amdgpu.tdm_base<i32> -> !amdgpu.tdm_descriptor
@@ -449,6 +515,33 @@ func.func @make_dma_base_invalid_barrier(%base: !amdgpu.tdm_base<i32>, %barrier:
// -----
+func.func @make_dma_descriptor_barrier_wrong_num_indices(%base: !amdgpu.tdm_base<i32>,
+ %barrier: memref<8x8x!amdgpu.ds_barrier_state, #gpu.address_space<workgroup>>,
+ %idx: index) {
+ // expected-error at +1 {{'amdgpu.make_dma_descriptor' op expected 2 atomic barrier indices, got 1}}
+ amdgpu.make_dma_descriptor %base
+ globalSize [64, 64] globalStride [64, 1] sharedSize [64, 64]
+ atomicBarrier(%barrier[%idx] : memref<8x8x!amdgpu.ds_barrier_state, #gpu.address_space<workgroup>>)
+ : !amdgpu.tdm_base<i32> -> !amdgpu.tdm_descriptor
+ return
+}
+
+// -----
+
+func.func @make_dma_descriptor_barrier_indices_without_address(
+ %base: !amdgpu.tdm_base<i32>, %idx: index) {
+ // expected-error at +1 {{'amdgpu.make_dma_descriptor' op atomic barrier indices require an atomic barrier address}}
+ %0 = "amdgpu.make_dma_descriptor"(%base, %idx) <{
+ global_static_sizes = array<i64: 64, 64>,
+ global_static_strides = array<i64: 64, 1>,
+ operandSegmentSizes = array<i32: 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0>,
+ shared_static_sizes = array<i64: 64, 64>
+ }> : (!amdgpu.tdm_base<i32>, index) -> !amdgpu.tdm_descriptor
+ return
+}
+
+// -----
+
// CHECK-LABEL: func @make_dma_descriptor_invalid_empty_strides
// CHECK-SAME: (%[[BASE:.+]]: !amdgpu.tdm_base<i32>)
func.func @make_dma_descriptor_invalid_empty_strides(%base: !amdgpu.tdm_base<i32>) {
@@ -500,6 +593,35 @@ func.func @make_gather_dma_descriptor_invalid_index_types(%base: !amdgpu.tdm_gat
// -----
+func.func @make_gather_dma_descriptor_barrier_wrong_num_indices(%base: !amdgpu.tdm_gather_base<i32, i16>,
+ %indices: vector<8xi16>,
+ %barrier: memref<8x8x!amdgpu.ds_barrier_state, #gpu.address_space<workgroup>>,
+ %idx: index) {
+ // expected-error at +1 {{'amdgpu.make_gather_dma_descriptor' op expected 2 atomic barrier indices, got 1}}
+ amdgpu.make_gather_dma_descriptor %base[%indices]
+ globalSize [4, 4] globalStride [4, 1] sharedSize [1, 2]
+ atomicBarrier(%barrier[%idx] : memref<8x8x!amdgpu.ds_barrier_state, #gpu.address_space<workgroup>>)
+ : !amdgpu.tdm_gather_base<i32, i16>, vector<8xi16> -> !amdgpu.tdm_descriptor
+ func.return
+}
+
+// -----
+
+func.func @make_gather_dma_descriptor_barrier_indices_without_address(
+ %base: !amdgpu.tdm_gather_base<i32, i16>, %indices: vector<8xi16>,
+ %idx: index) {
+ // expected-error at +1 {{'amdgpu.make_gather_dma_descriptor' op atomic barrier indices require an atomic barrier address}}
+ %0 = "amdgpu.make_gather_dma_descriptor"(%base, %indices, %idx) <{
+ global_static_sizes = array<i64: 4, 4>,
+ global_static_strides = array<i64: 4, 1>,
+ operandSegmentSizes = array<i32: 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0>,
+ shared_static_sizes = array<i64: 1, 2>
+ }> : (!amdgpu.tdm_gather_base<i32, i16>, vector<8xi16>, index) -> !amdgpu.tdm_descriptor
+ func.return
+}
+
+// -----
+
func.func @sparse_mfma_dense_not_double_sparse(%a: vector<4xf16>, %b: vector<4xf16>, %c: vector<4xf32>, %idx: vector<4xi8>) -> vector<4xf32> {
// expected-error at +1 {{'amdgpu.sparse_mfma' op operand #1 must be vector of 16-bit float values of length 8/16 or vector of bfloat16 type values of length 8/16 or vector of 8-bit signless integer values of length 16/32 or vector of f8E4M3FN type or f8E5M2 type values of length 16/32 or vector of f8E4M3FNUZ type or f8E5M2FNUZ type values of length 16/32, but got 'vector<4xf16>'}}
%d = amdgpu.sparse_mfma 16x16x32 %a * %b + %c sparse(%idx : vector<4xi8>) : vector<4xf16>, vector<4xf16>, vector<4xf32>
@@ -620,6 +742,15 @@ func.func @ds_barrier_init_non_workgroup(%barrier: memref<!amdgpu.ds_barrier_sta
// -----
+func.func @ds_barrier_init_wrong_num_indices(%barrier: memref<8x8x!amdgpu.ds_barrier_state, #gpu.address_space<workgroup>>,
+ %idx: index, %participants: i32) {
+ // expected-error at +1 {{'amdgpu.ds_barrier_init' op expected 2 barrier indices, got 1}}
+ amdgpu.ds_barrier_init %barrier[%idx], %participants : memref<8x8x!amdgpu.ds_barrier_state, #gpu.address_space<workgroup>>, i32
+ func.return
+}
+
+// -----
+
func.func @ds_barrier_poll_state_non_workgroup(%barrier: memref<!amdgpu.ds_barrier_state, #gpu.address_space<global>>) -> !amdgpu.ds_barrier_state {
// expected-error at +1 {{'amdgpu.ds_barrier_poll_state' op barrier must be in workgroup (LDS) memory}}
%state = amdgpu.ds_barrier_poll_state %barrier[] : memref<!amdgpu.ds_barrier_state, #gpu.address_space<global>> -> !amdgpu.ds_barrier_state
@@ -628,6 +759,24 @@ func.func @ds_barrier_poll_state_non_workgroup(%barrier: memref<!amdgpu.ds_barri
// -----
+func.func @ds_barrier_poll_state_wrong_num_indices(%barrier: memref<8x8x!amdgpu.ds_barrier_state, #gpu.address_space<workgroup>>,
+ %idx: index) -> !amdgpu.ds_barrier_state {
+ // expected-error at +1 {{'amdgpu.ds_barrier_poll_state' op expected 2 barrier indices, got 1}}
+ %state = amdgpu.ds_barrier_poll_state %barrier[%idx] : memref<8x8x!amdgpu.ds_barrier_state, #gpu.address_space<workgroup>> -> !amdgpu.ds_barrier_state
+ func.return %state : !amdgpu.ds_barrier_state
+}
+
+// -----
+
+func.func @ds_async_barrier_arrive_wrong_num_indices(%barrier: memref<8x8x!amdgpu.ds_barrier_state, #gpu.address_space<workgroup>>,
+ %idx: index) {
+ // expected-error at +1 {{'amdgpu.ds_async_barrier_arrive' op expected 2 barrier indices, got 1}}
+ amdgpu.ds_async_barrier_arrive %barrier[%idx] : memref<8x8x!amdgpu.ds_barrier_state, #gpu.address_space<workgroup>>
+ func.return
+}
+
+// -----
+
func.func @ds_barrier_arrive_non_workgroup(%barrier: memref<!amdgpu.ds_barrier_state, #amdgpu.address_space<fat_raw_buffer>>, %count: i64) -> !amdgpu.ds_barrier_state {
// expected-error at +1 {{'amdgpu.ds_barrier_arrive' op barrier must be in workgroup (LDS) memory}}
%old_state = amdgpu.ds_barrier_arrive %barrier[], %count : memref<!amdgpu.ds_barrier_state, #amdgpu.address_space<fat_raw_buffer>>, i64 -> !amdgpu.ds_barrier_state
@@ -636,6 +785,15 @@ func.func @ds_barrier_arrive_non_workgroup(%barrier: memref<!amdgpu.ds_barrier_s
// -----
+func.func @ds_barrier_arrive_wrong_num_indices(%barrier: memref<8x8x!amdgpu.ds_barrier_state, #gpu.address_space<workgroup>>,
+ %idx: index, %count: i64) -> !amdgpu.ds_barrier_state {
+ // expected-error at +1 {{'amdgpu.ds_barrier_arrive' op expected 2 barrier indices, got 1}}
+ %old_state = amdgpu.ds_barrier_arrive %barrier[%idx], %count : memref<8x8x!amdgpu.ds_barrier_state, #gpu.address_space<workgroup>>, i64 -> !amdgpu.ds_barrier_state
+ func.return %old_state : !amdgpu.ds_barrier_state
+}
+
+// -----
+
func.func @sparse_wmma_invalid_m(%a: vector<8xf16>, %b: vector<16xf16>, %c: vector<8xf32>, %idx: vector<4xi8>) -> vector<8xf32> {
// expected-error at +1 {{'amdgpu.sparse_wmma' op attribute 'm' failed to satisfy constraint: 32-bit signless integer attribute whose value is one of {16}}}
%d = amdgpu.sparse_wmma 32x16x32 %a * %b + %c sparse(%idx : vector<4xi8>) : vector<8xf16>, vector<16xf16>, vector<8xf32>
@@ -778,7 +936,7 @@ func.func @global_prefetch_wrong_num_indices(%src: memref<64x64xf16, #gpu.addres
// GlobalPrefetchOp: number of indices must match source shape rank
func.func @global_prefetch_wrong_num_indices(%src: memref<64x64xf16, #gpu.address_space<global>>, %i: i64) {
- // expected-error at +1 {{'amdgpu.global_prefetch' op the number of indices must match the source shape size}}
+ // expected-error at +1 {{'amdgpu.global_prefetch' op expected 2 source indices, got 1}}
amdgpu.global_prefetch %src[%i] RT DEV : memref<64x64xf16, #gpu.address_space<global>>
func.return
}
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