[Mlir-commits] [mlir] [mlir][arith] Add LUT-based lowering of arith.extf for FP8 to F32. (PR #196321)

[Jakub Kuderski]

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kuhar wrote:

Could you cut it down in half by separating out the sign bit? IIRC, this is what @Muzammiluddin-Syed-ECE and @krzysz00 implemented for fp6/fp4 in https://github.com/llvm/llvm-project/pull/144157

https://github.com/llvm/llvm-project/pull/196321