[Mlir-commits] [mlir] [AMDGPU] Fix legacy gfx942 bf16 sparse mfma lowering in gfx950 (PR #195977)
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Tue May 5 19:08:52 PDT 2026
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diff --git a/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp b/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
index 67ca6052c..8b9b3e194 100644
--- a/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+++ b/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
@@ -1702,7 +1702,11 @@ struct SparseMFMAOpLowering : public ConvertOpToLLVMPattern<SparseMFMAOp> {
if (!maybeIntrinsic.has_value())
return op.emitOpError(
"no intrinsic matching sparse MFMA on the given chipset");
- bool isGfx942BF16 = (*maybeIntrinsic == ROCDL::smfmac_f32_16x16x32_bf16::getOperationName() || *maybeIntrinsic == ROCDL::smfmac_f32_32x32x16_bf16::getOperationName());
+ bool isGfx942BF16 =
+ (*maybeIntrinsic ==
+ ROCDL::smfmac_f32_16x16x32_bf16::getOperationName() ||
+ *maybeIntrinsic ==
+ ROCDL::smfmac_f32_32x32x16_bf16::getOperationName());
bool isGfx950 = (chipset >= kGfx950) && !isGfx942BF16;
Value a = convertPackedVectorOperand(rewriter, loc, adaptor.getSourceA(),
@@ -1711,7 +1715,6 @@ struct SparseMFMAOpLowering : public ConvertOpToLLVMPattern<SparseMFMAOp> {
isGfx950);
Value c = adaptor.getDestC();
-
// Bitcast sparse indices from vector<4xi8> or vector<2xi16> to i32.
// gfx950 8-bit variants already carry the index as i32; skip the bitcast.
Value sparseIdx = adaptor.getSparseIdx();
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https://github.com/llvm/llvm-project/pull/195977
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