[Mlir-commits] [mlir] 32c6548 - [mlir][NFC] Fix typo (flattend => flattened) (#195780)

[llvmlistbot at llvm.org]

Author: Kevin Boyette
Date: 2026-05-05T15:02:59+08:00
New Revision: 32c6548546373726ac252967db78abbb2b93fcbe

URL: https://github.com/llvm/llvm-project/commit/32c6548546373726ac252967db78abbb2b93fcbe
DIFF: https://github.com/llvm/llvm-project/commit/32c6548546373726ac252967db78abbb2b93fcbe.diff

LOG: [mlir][NFC] Fix typo (flattend => flattened) (#195780)

Added: 
    

Modified: 
    mlir/include/mlir/IR/AffineExprVisitor.h
    mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
    mlir/lib/IR/BuiltinAttributeInterfaces.cpp

Removed: 
    


################################################################################
diff  --git a/mlir/include/mlir/IR/AffineExprVisitor.h b/mlir/include/mlir/IR/AffineExprVisitor.h
index 1826f5fd8ad35..ccf62fc80f748 100644
--- a/mlir/include/mlir/IR/AffineExprVisitor.h
+++ b/mlir/include/mlir/IR/AffineExprVisitor.h
@@ -354,11 +354,11 @@ class AffineExprVisitor<SubClass, LogicalResult>
 class SimpleAffineExprFlattener
     : public AffineExprVisitor<SimpleAffineExprFlattener, LogicalResult> {
 public:
-  // Flattend expression layout: [dims, symbols, locals, constant]
+  // Flattened expression layout: [dims, symbols, locals, constant]
   // Stack that holds the LHS and RHS operands while visiting a binary op expr.
-  // In future, consider adding a prepass to determine how big the SmallVector's
-  // will be, and linearize this to std::vector<int64_t> to prevent
-  // SmallVector moves on re-allocation.
+  // In the future, consider adding a prepass to determine how big the
+  // SmallVector's will be, and linearize this to std::vector<int64_t> to
+  // prevent SmallVector moves on re-allocation.
   std::vector<SmallVector<int64_t, 8>> operandExprStack;
 
   unsigned numDims;

diff  --git a/mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp b/mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
index c1d5794bdb82c..e92b109c2223e 100644
--- a/mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
+++ b/mlir/lib/Dialect/XeGPU/IR/XeGPUDialect.cpp
@@ -794,19 +794,19 @@ SliceAttr SliceAttr::flatten() const {
   SmallVector<int64_t> indices =
       llvm::to_vector(llvm::seq<int64_t>(0, layoutAttr.getRank()));
 
-  // get remaining dims (flattend) by applying slice ops with all slicedDims
+  // get remaining dims (flattened) by applying slice ops with all slicedDims
   SmallVector<int64_t> remainingDims(indices);
   for (auto dim : llvm::reverse(slicedDims))
     remainingDims = XeGPUDialect::slice(llvm::ArrayRef<int64_t>(remainingDims),
                                         dim.asArrayRef());
 
-  // get flattend sliced dims by applying slice ops with the remaining dims
-  SmallVector<int64_t> flattendDims = XeGPUDialect::slice(
+  // get flattened sliced dims by applying slice ops with the remaining dims
+  SmallVector<int64_t> flattenedDims = XeGPUDialect::slice(
       llvm::ArrayRef<int64_t>(indices), llvm::ArrayRef<int64_t>(remainingDims));
 
   return xegpu::SliceAttr::get(
       getContext(), layoutAttr,
-      DenseI64ArrayAttr::get(getContext(), flattendDims));
+      DenseI64ArrayAttr::get(getContext(), flattenedDims));
 }
 
 FailureOr<SmallVector<Value>>

diff  --git a/mlir/lib/IR/BuiltinAttributeInterfaces.cpp b/mlir/lib/IR/BuiltinAttributeInterfaces.cpp
index 9e8ce4ca3a902..ebf44075479dc 100644
--- a/mlir/lib/IR/BuiltinAttributeInterfaces.cpp
+++ b/mlir/lib/IR/BuiltinAttributeInterfaces.cpp
@@ -57,7 +57,7 @@ uint64_t ElementsAttr::getFlattenedIndex(Type type, ArrayRef<uint64_t> index) {
   assert(isValidIndex(shapeType, index) &&
          "expected valid multi-dimensional index");
 
-  // Reduce the provided multidimensional index into a flattended 1D row-major
+  // Reduce the provided multidimensional index into a flattened 1D row-major
   // index.
   auto rank = shapeType.getRank();
   ArrayRef<int64_t> shape = shapeType.getShape();