[Mlir-commits] [mlir] [mlir][SPIR-V] Add support for SPV_INTEL_long_composites extension (PR #195685)
llvmlistbot at llvm.org
llvmlistbot at llvm.org
Mon May 4 09:36:14 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-mlir-spirv
Author: Arseniy Obolenskiy (aobolensk)
<details>
<summary>Changes</summary>
Add serialization and deserialization support for the SPV_INTEL_long_composites extension, which allows splitting composite/struct instructions that exceed the SPIR-V 16-bit word count limit (65535 words) into a head instruction followed by one or more continuation instructions
Note: Patch size is quite big due to the test cases, they require 65535+ operations to perform the needed opcode
---
Patch is 4.56 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/195685.diff
11 Files Affected:
- (modified) mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td (+8)
- (modified) mlir/include/mlir/Target/SPIRV/SPIRVBinaryUtils.h (+20)
- (modified) mlir/lib/Target/SPIRV/Deserialization/DeserializeOps.cpp (+34)
- (modified) mlir/lib/Target/SPIRV/Deserialization/Deserializer.h (+9)
- (modified) mlir/lib/Target/SPIRV/Serialization/SerializeOps.cpp (+2-2)
- (modified) mlir/lib/Target/SPIRV/Serialization/Serializer.cpp (+83-5)
- (modified) mlir/lib/Target/SPIRV/Serialization/Serializer.h (+15)
- (added) mlir/test/Target/SPIRV/long-composites-composite-construct.mlir (+19)
- (added) mlir/test/Target/SPIRV/long-composites-constant-array.mlir (+19)
- (added) mlir/test/Target/SPIRV/long-composites-spec-constant-composite.mlir (+65555)
- (added) mlir/test/Target/SPIRV/long-composites-type-struct.mlir (+16)
``````````diff
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
index b5cc5f6ba8cb5..2c5dc9131a5e1 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
@@ -4668,6 +4668,10 @@ def SPIRV_OC_OpSubgroupBlockReadINTEL : I32EnumAttrCase<"OpSubgroupBlock
def SPIRV_OC_OpSubgroupBlockWriteINTEL : I32EnumAttrCase<"OpSubgroupBlockWriteINTEL", 5576>;
def SPIRV_OC_OpAssumeTrueKHR : I32EnumAttrCase<"OpAssumeTrueKHR", 5630>;
def SPIRV_OC_OpAtomicFAddEXT : I32EnumAttrCase<"OpAtomicFAddEXT", 6035>;
+def SPIRV_OC_OpTypeStructContinuedINTEL : I32EnumAttrCase<"OpTypeStructContinuedINTEL", 6090>;
+def SPIRV_OC_OpConstantCompositeContinuedINTEL : I32EnumAttrCase<"OpConstantCompositeContinuedINTEL", 6091>;
+def SPIRV_OC_OpSpecConstantCompositeContinuedINTEL : I32EnumAttrCase<"OpSpecConstantCompositeContinuedINTEL", 6092>;
+def SPIRV_OC_OpCompositeConstructContinuedINTEL : I32EnumAttrCase<"OpCompositeConstructContinuedINTEL", 6096>;
def SPIRV_OC_OpConvertFToBF16INTEL : I32EnumAttrCase<"OpConvertFToBF16INTEL", 6116>;
def SPIRV_OC_OpConvertBF16ToFINTEL : I32EnumAttrCase<"OpConvertBF16ToFINTEL", 6117>;
def SPIRV_OC_OpControlBarrierArriveINTEL : I32EnumAttrCase<"OpControlBarrierArriveINTEL", 6142>;
@@ -4789,6 +4793,10 @@ def SPIRV_OpcodeAttr :
SPIRV_OC_OpEmitMeshTasksEXT, SPIRV_OC_OpSetMeshOutputsEXT,
SPIRV_OC_OpSubgroupBlockReadINTEL, SPIRV_OC_OpSubgroupBlockWriteINTEL,
SPIRV_OC_OpAssumeTrueKHR, SPIRV_OC_OpAtomicFAddEXT,
+ SPIRV_OC_OpTypeStructContinuedINTEL,
+ SPIRV_OC_OpConstantCompositeContinuedINTEL,
+ SPIRV_OC_OpSpecConstantCompositeContinuedINTEL,
+ SPIRV_OC_OpCompositeConstructContinuedINTEL,
SPIRV_OC_OpConvertFToBF16INTEL, SPIRV_OC_OpConvertBF16ToFINTEL,
SPIRV_OC_OpControlBarrierArriveINTEL, SPIRV_OC_OpControlBarrierWaitINTEL,
SPIRV_OC_OpGroupIMulKHR, SPIRV_OC_OpGroupFMulKHR,
diff --git a/mlir/include/mlir/Target/SPIRV/SPIRVBinaryUtils.h b/mlir/include/mlir/Target/SPIRV/SPIRVBinaryUtils.h
index 4a4116312981a..34aa774310343 100644
--- a/mlir/include/mlir/Target/SPIRV/SPIRVBinaryUtils.h
+++ b/mlir/include/mlir/Target/SPIRV/SPIRVBinaryUtils.h
@@ -17,6 +17,7 @@
#include "mlir/Support/LLVM.h"
#include <cstdint>
+#include <optional>
namespace mlir {
namespace spirv {
@@ -58,6 +59,25 @@ inline StringRef decodeStringLiteral(ArrayRef<uint32_t> words,
return str;
}
+/// Returns the SPV_INTEL_long_composites continuation opcode that may follow
+/// `parent`, or std::nullopt if `parent` is not a splittable composite/struct
+/// op.
+inline std::optional<spirv::Opcode>
+getContinuationOpcode(spirv::Opcode parent) {
+ switch (parent) {
+ case spirv::Opcode::OpTypeStruct:
+ return spirv::Opcode::OpTypeStructContinuedINTEL;
+ case spirv::Opcode::OpConstantComposite:
+ return spirv::Opcode::OpConstantCompositeContinuedINTEL;
+ case spirv::Opcode::OpSpecConstantComposite:
+ return spirv::Opcode::OpSpecConstantCompositeContinuedINTEL;
+ case spirv::Opcode::OpCompositeConstruct:
+ return spirv::Opcode::OpCompositeConstructContinuedINTEL;
+ default:
+ return std::nullopt;
+ }
+}
+
} // namespace spirv
} // namespace mlir
diff --git a/mlir/lib/Target/SPIRV/Deserialization/DeserializeOps.cpp b/mlir/lib/Target/SPIRV/Deserialization/DeserializeOps.cpp
index c12647d4255aa..d58b211eb7891 100644
--- a/mlir/lib/Target/SPIRV/Deserialization/DeserializeOps.cpp
+++ b/mlir/lib/Target/SPIRV/Deserialization/DeserializeOps.cpp
@@ -125,11 +125,45 @@ LogicalResult spirv::Deserializer::sliceInstruction(
return success();
}
+void spirv::Deserializer::mergeLongCompositeContinuations(
+ spirv::Opcode opcode, ArrayRef<uint32_t> &operands,
+ SmallVectorImpl<uint32_t> &mergedStorage) {
+ std::optional<spirv::Opcode> continuationOp = getContinuationOpcode(opcode);
+ if (!continuationOp)
+ return;
+
+ auto binarySize = binary.size();
+ auto isNextContinuation = [&]() {
+ if (curOffset >= binarySize)
+ return false;
+ uint32_t wordCount = binary[curOffset] >> 16;
+ if (wordCount == 0 || curOffset + wordCount > binarySize)
+ return false;
+ return extractOpcode(binary[curOffset]) == *continuationOp;
+ };
+
+ if (!isNextContinuation())
+ return;
+
+ mergedStorage.assign(operands.begin(), operands.end());
+ do {
+ spirv::Opcode contOpcode;
+ ArrayRef<uint32_t> contOperands;
+ if (failed(sliceInstruction(contOpcode, contOperands, *continuationOp)))
+ return;
+ mergedStorage.append(contOperands.begin(), contOperands.end());
+ } while (isNextContinuation());
+ operands = mergedStorage;
+}
+
LogicalResult spirv::Deserializer::processInstruction(
spirv::Opcode opcode, ArrayRef<uint32_t> operands, bool deferInstructions) {
LLVM_DEBUG(logger.startLine() << "[inst] processing instruction "
<< spirv::stringifyOpcode(opcode) << "\n");
+ SmallVector<uint32_t, 0> mergedStorage;
+ mergeLongCompositeContinuations(opcode, operands, mergedStorage);
+
// First dispatch all the instructions whose opcode does not correspond to
// those that have a direct mirror in the SPIR-V dialect
switch (opcode) {
diff --git a/mlir/lib/Target/SPIRV/Deserialization/Deserializer.h b/mlir/lib/Target/SPIRV/Deserialization/Deserializer.h
index 9725c63deb8c2..c867ecb9f8827 100644
--- a/mlir/lib/Target/SPIRV/Deserialization/Deserializer.h
+++ b/mlir/lib/Target/SPIRV/Deserialization/Deserializer.h
@@ -516,6 +516,15 @@ class Deserializer {
sliceInstruction(spirv::Opcode &opcode, ArrayRef<uint32_t> &operands,
std::optional<spirv::Opcode> expectedOpcode = std::nullopt);
+ /// If `opcode` is a SPV_INTEL_long_composites splittable opcode and the
+ /// next binary instruction(s) are matching `*ContinuedINTEL` ops, consumes
+ /// them and rebinds `operands` to a buffer (held in `mergedStorage`)
+ /// containing the parent + continuation operands concatenated.
+ void
+ mergeLongCompositeContinuations(spirv::Opcode opcode,
+ ArrayRef<uint32_t> &operands,
+ SmallVectorImpl<uint32_t> &mergedStorage);
+
/// Processes a SPIR-V instruction with the given `opcode` and `operands`.
/// This method is the main entrance for handling SPIR-V instruction; it
/// checks the instruction opcode and dispatches to the corresponding handler.
diff --git a/mlir/lib/Target/SPIRV/Serialization/SerializeOps.cpp b/mlir/lib/Target/SPIRV/Serialization/SerializeOps.cpp
index a2c942d4188e7..841fc55a8627a 100644
--- a/mlir/lib/Target/SPIRV/Serialization/SerializeOps.cpp
+++ b/mlir/lib/Target/SPIRV/Serialization/SerializeOps.cpp
@@ -121,8 +121,8 @@ Serializer::processSpecConstantCompositeOp(spirv::SpecConstantCompositeOp op) {
operands.push_back(constituentID);
}
- encodeInstructionInto(typesGlobalValues,
- spirv::Opcode::OpSpecConstantComposite, operands);
+ encodeInstructionWithContinuationInto(
+ typesGlobalValues, spirv::Opcode::OpSpecConstantComposite, operands);
specConstIDMap[op.getSymName()] = resultID;
return processName(resultID, op.getSymName());
diff --git a/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp b/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
index e29a437cca87f..4fdd886304bce 100644
--- a/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
+++ b/mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
@@ -213,6 +213,42 @@ void Serializer::processCapability() {
{static_cast<uint32_t>(cap)});
}
+void Serializer::addLongCompositesCapability() {
+ if (longCompositesEmitted)
+ return;
+ longCompositesEmitted = true;
+ encodeInstructionInto(
+ capabilities, spirv::Opcode::OpCapability,
+ {static_cast<uint32_t>(spirv::Capability::LongCompositesINTEL)});
+ SmallVector<uint32_t, 8> extName;
+ spirv::encodeStringLiteralInto(
+ extName,
+ spirv::stringifyExtension(spirv::Extension::SPV_INTEL_long_composites));
+ encodeInstructionInto(extensions, spirv::Opcode::OpExtension, extName);
+}
+
+void Serializer::encodeInstructionWithContinuationInto(
+ SmallVectorImpl<uint32_t> &binary, spirv::Opcode op,
+ ArrayRef<uint32_t> operands) {
+ if (1 + operands.size() <= spirv::kMaxWordCount) {
+ encodeInstructionInto(binary, op, operands);
+ return;
+ }
+
+ std::optional<spirv::Opcode> continuationOp =
+ spirv::getContinuationOpcode(op);
+ assert(continuationOp && "op is not a splittable composite/struct opcode");
+
+ const unsigned chunk = spirv::kMaxWordCount - 1;
+ encodeInstructionInto(binary, op, operands.take_front(chunk));
+ for (ArrayRef<uint32_t> rest = operands.drop_front(chunk); !rest.empty();
+ rest = rest.drop_front(std::min<size_t>(rest.size(), chunk))) {
+ encodeInstructionInto(binary, *continuationOp, rest.take_front(chunk));
+ }
+
+ addLongCompositesCapability();
+}
+
void Serializer::processDebugInfo() {
if (!options.emitDebugInfo)
return;
@@ -560,7 +596,11 @@ Serializer::processTypeImpl(Location loc, Type type, uint32_t &typeID,
typeIDMap[type] = typeID;
- encodeInstructionInto(typesGlobalValues, typeEnum, operands);
+ if (typeEnum == spirv::Opcode::OpTypeStruct)
+ encodeInstructionWithContinuationInto(typesGlobalValues, typeEnum,
+ operands);
+ else
+ encodeInstructionInto(typesGlobalValues, typeEnum, operands);
if (recursiveStructInfos.count(type) != 0) {
// This recursive struct type is emitted already, now the OpTypePointer
@@ -1019,8 +1059,8 @@ uint32_t Serializer::prepareArrayConstant(Location loc, Type constType,
return 0;
}
}
- spirv::Opcode opcode = spirv::Opcode::OpConstantComposite;
- encodeInstructionInto(typesGlobalValues, opcode, operands);
+ encodeInstructionWithContinuationInto(
+ typesGlobalValues, spirv::Opcode::OpConstantComposite, operands);
return resultID;
}
@@ -1099,8 +1139,8 @@ Serializer::prepareDenseElementsConstant(Location loc, Type constType,
}
}
}
- spirv::Opcode opcode = spirv::Opcode::OpConstantComposite;
- encodeInstructionInto(typesGlobalValues, opcode, operands);
+ encodeInstructionWithContinuationInto(
+ typesGlobalValues, spirv::Opcode::OpConstantComposite, operands);
return resultID;
}
@@ -1600,6 +1640,9 @@ LogicalResult Serializer::processOperation(Operation *opInst) {
return processBranchConditionalOp(op);
})
.Case([&](spirv::ConstantOp op) { return processConstantOp(op); })
+ .Case([&](spirv::CompositeConstructOp op) {
+ return processCompositeConstructOp(op);
+ })
.Case([&](spirv::EXTConstantCompositeReplicateOp op) {
return processConstantCompositeReplicateOp(op);
})
@@ -1640,6 +1683,41 @@ LogicalResult Serializer::processOperation(Operation *opInst) {
[&](Operation *op) { return dispatchToAutogenSerialization(op); });
}
+LogicalResult
+Serializer::processCompositeConstructOp(spirv::CompositeConstructOp op) {
+ Location loc = op.getLoc();
+
+ uint32_t resultTypeID = 0;
+ if (failed(processType(loc, op.getType(), resultTypeID)))
+ return failure();
+
+ uint32_t resultID = getNextID();
+ valueIDMap[op.getResult()] = resultID;
+
+ SmallVector<uint32_t, 8> operands;
+ operands.reserve(2 + op.getConstituents().size());
+ operands.push_back(resultTypeID);
+ operands.push_back(resultID);
+ for (Value constituent : op.getConstituents()) {
+ uint32_t id = getValueID(constituent);
+ assert(id && "use before def!");
+ operands.push_back(id);
+ }
+
+ if (failed(emitDebugLine(functionBody, loc)))
+ return failure();
+
+ encodeInstructionWithContinuationInto(
+ functionBody, spirv::Opcode::OpCompositeConstruct, operands);
+
+ for (auto attr : op->getAttrs()) {
+ if (failed(processDecoration(loc, resultID, attr)))
+ return failure();
+ }
+
+ return success();
+}
+
LogicalResult Serializer::processOpWithoutGrammarAttr(Operation *op,
StringRef extInstSet,
uint32_t opcode) {
diff --git a/mlir/lib/Target/SPIRV/Serialization/Serializer.h b/mlir/lib/Target/SPIRV/Serialization/Serializer.h
index eb5ac0d60038e..e43556fab9acf 100644
--- a/mlir/lib/Target/SPIRV/Serialization/Serializer.h
+++ b/mlir/lib/Target/SPIRV/Serialization/Serializer.h
@@ -104,10 +104,23 @@ class Serializer {
LogicalResult processExtension();
+ /// Encodes `op` + `operands` into `binary`, splitting via the
+ /// SPV_INTEL_long_composites continuation opcode when the total word count
+ /// would exceed kMaxWordCount. `op` must be a splittable composite/struct
+ /// opcode (see getContinuationOpcode). The capability and extension are
+ /// emitted lazily on first split.
+ void encodeInstructionWithContinuationInto(SmallVectorImpl<uint32_t> &binary,
+ spirv::Opcode op,
+ ArrayRef<uint32_t> operands);
+
+ void addLongCompositesCapability();
+
void processMemoryModel();
LogicalResult processConstantOp(spirv::ConstantOp op);
+ LogicalResult processCompositeConstructOp(spirv::CompositeConstructOp op);
+
LogicalResult processConstantCompositeReplicateOp(
spirv::EXTConstantCompositeReplicateOp op);
@@ -387,6 +400,8 @@ class Serializer {
/// The next available result <id>.
uint32_t nextID = 1;
+ bool longCompositesEmitted = false;
+
// The following are for different SPIR-V instruction sections. They follow
// the logical layout of a SPIR-V module.
diff --git a/mlir/test/Target/SPIRV/long-composites-composite-construct.mlir b/mlir/test/Target/SPIRV/long-composites-composite-construct.mlir
new file mode 100644
index 0000000000000..52b999ffe681b
--- /dev/null
+++ b/mlir/test/Target/SPIRV/long-composites-composite-construct.mlir
@@ -0,0 +1,19 @@
+// RUN: mlir-translate -no-implicit-module -test-spirv-roundtrip %s | FileCheck %s
+
+// SPV_INTEL_long_composites: composites whose binary form would
+// exceed the SPIR-V 16-bit word-count limit are split into a
+// parent + *ContinuedINTEL ops on serialization, and merged back
+// on deserialization. The round-trip preserves the IR.
+// The composite below has 65540 operands -- past the threshold.
+
+// CHECK-LABEL: spirv.module Logical GLSL450
+// CHECK-SAME: LongCompositesINTEL
+// CHECK-SAME: SPV_INTEL_long_composites
+// CHECK: spirv.func @long_composite_construct
+// CHECK: spirv.CompositeConstruct
+spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Shader, Linkage, Int8, LongCompositesINTEL], [SPV_INTEL_long_composites]> {
+ spirv.func @long_composite_construct(%arg0: i8) -> (!spirv.array<65540 x i8>) "None" {
+ %0 = spirv.CompositeConstruct %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, %arg0, 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[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/195685
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