[Mlir-commits] [mlir] [mlir][ROCDL] Add rocdl.wave.barrier (PR #195357)

[Krzysztof Drewniak]

https://github.com/krzysz00 created https://github.com/llvm/llvm-project/pull/195357

None

>From 86b98a03ee20c445a8c04048b4590f945d9a52de Mon Sep 17 00:00:00 2001
From: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: Fri, 1 May 2026 20:42:21 +0000
Subject: [PATCH] [mlir][ROCDL] Add rocdl.wave.barrier

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply at anthropic.com>
---
 mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td | 13 +++++++++++++
 mlir/test/Dialect/LLVMIR/rocdl.mlir          |  6 ++++++
 mlir/test/Target/LLVMIR/rocdl.mlir           |  7 +++++++
 3 files changed, 26 insertions(+)

diff --git a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
index a9a5d0f983538..14e3a359cab3a 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
@@ -536,6 +536,19 @@ def ROCDL_BarrierOp : ROCDL_Op<"barrier"> {
   let assemblyFormat = "attr-dict";
 }
 
+def ROCDL_WaveBarrierOp : ROCDL_ConcreteNonMemIntrOp<"wave.barrier", [], 0> {
+  let assemblyFormat = "attr-dict";
+  let description = [{
+    Insert a wave-level (subgroup) barrier. Synchronizes lanes within a
+    single wave/wavefront without any memory ordering guarantees.
+
+    Example:
+    ```mlir
+    rocdl.wave.barrier
+    ```
+  }];
+}
+
 def ROCDLGlobalBuffer : LLVM_PointerInAddressSpace<1>;
 def ROCDLBufferLDS : LLVM_PointerInAddressSpace<3>;
 
diff --git a/mlir/test/Dialect/LLVMIR/rocdl.mlir b/mlir/test/Dialect/LLVMIR/rocdl.mlir
index e8c2527313c43..db1cefe86dfc6 100644
--- a/mlir/test/Dialect/LLVMIR/rocdl.mlir
+++ b/mlir/test/Dialect/LLVMIR/rocdl.mlir
@@ -111,6 +111,12 @@ func.func @rocdl.barrier() {
   llvm.return
 }
 
+func.func @rocdl.wave_barrier() {
+  // CHECK: rocdl.wave.barrier
+  rocdl.wave.barrier
+  llvm.return
+}
+
 func.func @rocdl.sched_barrier() {
   // CHECK: rocdl.sched.barrier
   rocdl.sched.barrier 0
diff --git a/mlir/test/Target/LLVMIR/rocdl.mlir b/mlir/test/Target/LLVMIR/rocdl.mlir
index 7ea554b897646..9e1d98b8422da 100644
--- a/mlir/test/Target/LLVMIR/rocdl.mlir
+++ b/mlir/test/Target/LLVMIR/rocdl.mlir
@@ -262,6 +262,13 @@ llvm.func @rocdl.barrier() {
   llvm.return
 }
 
+llvm.func @rocdl.wave_barrier() {
+  // CHECK-LABEL: rocdl.wave_barrier
+  // CHECK-NEXT: call void @llvm.amdgcn.wave.barrier()
+  rocdl.wave.barrier
+  llvm.return
+}
+
 llvm.func @rocdl.s.barrier.init(%ptr : !llvm.ptr<3>) {
   // CHECK-LABEL: rocdl.s.barrier.init
   // CHECK: call void @llvm.amdgcn.s.barrier.init(ptr addrspace(3) %{{.*}}, i32 1)