[Mlir-commits] [mlir] [MLIR][AMDGPU] Add amdgpu.global_transpose_load op for RDNA4 global memory transpose loads (PR #195287)

[Krzysztof Drewniak]

================
@@ -1449,6 +1449,45 @@ def AMDGPU_TransposeLoadOp :
   let hasVerifier = 1;
 }
 
+def AMDGPU_GlobalTransposeLoadOp :
+    AMDGPU_Op<"global_transpose_load", [SameVariadicOperandSize]>,
+    Arguments<(ins Arg<AnyMemRef, "buffer to transpose load from", [MemRead]>:$src,
+                      Variadic<Index>:$srcIndices)>,
+    Results<(outs AnyTypeOf<[AnyVectorOfNonZeroRank]>:$result)> {
+  let summary = "MLIR wrapper for RDNA4 global memory transpose load instructions";
+  let description = [{
+    The `amdgpu.global_transpose_load` op is a wrapper around the
+    `global_load_tr` family of instructions introduced in RDNA4 (gfx1250+).
+
+    Each thread reads a column of a matrix stored in global memory and receives
+    the corresponding row of the transposed matrix in its result register.
+    The subgroup collectively performs a transpose of the tile.
+
+    This op is a direct wrapper around the ROCDL `global.load.tr` family
+    intrinsics. Refer to the RDNA4 ISA documentation for exact semantics.
+
+    Format example:
+    ```
+    %0 = amdgpu.global_transpose_load %src[%i, %j]
+           : memref<128x256xf16, #gpu.address_space<global>> -> vector<8xf16>
+    ```
+    Operands:
+    * `$src`: Global address space memref to read from.
+    * `$srcIndices`: indices into `$src` for this thread.
+    * `$result`: register this transpose load instruction writes to.
+
+    Valid (element bits, num elements) pairs:
+    * (8, 8)   -> global_load_tr_b64
+    * (16, 8)  -> global_load_tr_b128
+
+    Note: Lowering is only supported on gfx1250 and up.
----------------
krzysz00 wrote:

Can you add a note requiring the indices to be non-negative in in-bounds, matching the memref.load constraints?

https://github.com/llvm/llvm-project/pull/195287