[Mlir-commits] [mlir] [MLIR][NVVM] Add nvvm.addf and nvvm.subf Ops (PR #179162)

Guray Ozen llvmlistbot at llvm.org
Thu Mar 5 04:52:59 PST 2026


================

----------------
grypp wrote:

for `vector<2xf64>` the compiler generates 2xPTX instructions, right? That means we are doing a slightly higher-level lowering here. I’m not sure this is consistent with the rest of NVVM. 

https://github.com/llvm/llvm-project/pull/179162


More information about the Mlir-commits mailing list