[Mlir-commits] [mlir] [XeVM] Add translation for XeVM cache-control attributes. (PR #181856)

[Md Abdullah Shahneous Bari]

================
@@ -17,19 +17,148 @@
 #include "mlir/IR/Operation.h"
 #include "mlir/Target/LLVMIR/ModuleTranslation.h"
 
+#include "mlir/Support/LLVM.h"
 #include "llvm/ADT/TypeSwitch.h"
+#include "llvm/IR/ConstantRange.h"
 #include "llvm/IR/Constants.h"
+#include "llvm/IR/DebugInfoMetadata.h"
+#include "llvm/IR/DebugLoc.h"
+#include "llvm/IR/GlobalVariable.h"
+#include "llvm/IR/IRBuilder.h"
 #include "llvm/IR/LLVMContext.h"
 #include "llvm/IR/Metadata.h"
-
-#include "llvm/IR/ConstantRange.h"
-#include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/Module.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace mlir;
 using namespace mlir::LLVM;
 
 namespace {
+//===----------------------------------------------------------------------===//
+// Utility functions for the translation
+//===----------------------------------------------------------------------===//
+// Extract the source filename from the debug location of \p inst, if available.
+static std::string getSourceFilename(const llvm::Instruction *inst) {
+  if (const llvm::DebugLoc &dbgLoc = inst->getDebugLoc()) {
+    if (auto *loc = dbgLoc.get()) {
+      if (llvm::DIFile *file = loc->getFile()) {
+        if (!file->getDirectory().empty())
+          return (file->getDirectory() + "/" + file->getFilename()).str();
+        return file->getFilename().str();
+      }
+    }
+  }
+  return "";
+}
+
+// Build one cache-control payload string per attribute.
+//
+// Each mlir::Attribute is expected to be an ArrayAttr of (at least) 3
+// IntegerAttr values: [SPIR-V token number of that attribute, value for L1
+// cache, value for L3 cache].
+//
+// A single entry produces a string that appears in LLVM IR as:
+//   {6442:\220,1\22}\00
+static llvm::SmallVector<std::string>
+buildCacheControlPayloads(llvm::ArrayRef<mlir::Attribute> attrs) {
+  llvm::SmallVector<std::string> payloads;
+  llvm::StringMap<bool> seen;
+
+  for (mlir::Attribute a : attrs) {
+    auto arr = mlir::dyn_cast<mlir::ArrayAttr>(a);
+    if (!arr)
+      continue;
+
+    auto vals = arr.getValue();
+    // Assert that the attribute has at most 4 integer values: [SPIR-V token, L1
+    // value, L3 value, optional extra value].
+    assert(vals.size() <= 4 &&
+           "Expected at most 4 integer values in cache control attribute.");
+
+    //  Although the caching value is allowed for 3 levels (L1, L2, L3), current
+    //  Intel GPUs only have L1, and L3. So we only use L1 and L3 values. The L2
+    //  value is ignored.
+    auto firstAttr = mlir::dyn_cast<mlir::IntegerAttr>(vals[0]); // Token number
+    auto secondAttr = mlir::dyn_cast<mlir::IntegerAttr>(vals[1]); // L1 value
+    // L2 value is ignored: vals[2]
+    auto thirdAttr = mlir::dyn_cast<mlir::IntegerAttr>(vals[3]); // L3 value
+
+    if (!firstAttr || !secondAttr || !thirdAttr)
+      continue;
+
+    uint64_t first = firstAttr.getValue().getZExtValue();
+    uint64_t second = secondAttr.getValue().getZExtValue();
+    uint64_t third = thirdAttr.getValue().getZExtValue();
+
+    // Produce: {FIRST:\22SECOND,THIRD\22}
+    // where \22 is the 0x22 byte ("), which LLVM IR prints as \22.
+    // The null terminator (\00) is added by ConstantDataArray::getString.
+    std::string entry;
+    entry.push_back('{');
+    entry += std::to_string(first);
+    entry.push_back(':');
+    entry.push_back('"'); // 0x22 → prints as \22 in LLVM IR
+    entry += std::to_string(second);
+    entry.push_back(',');
+    entry += std::to_string(third);
+    entry.push_back('"'); // 0x22 → prints as \22 in LLVM IR
+    entry.push_back('}');
----------------
mshahneo wrote:

Thanks, done.

https://github.com/llvm/llvm-project/pull/181856