[Mlir-commits] [llvm] [mlir] [IR] Split Br into UncondBr and CondBr (PR #184027)

[Nikita Popov]

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@@ -732,7 +732,8 @@ bool TypePromotionImpl::isSupportedValue(Value *V) {
              !GenerateSignBits(I);
     case Instruction::GetElementPtr:
     case Instruction::Store:
-    case Instruction::Br:
+    case Instruction::UncondBr:
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nikic wrote:

Just CondBr is probably sufficient here, as Br has neither (value) operands nor results.

https://github.com/llvm/llvm-project/pull/184027