[Mlir-commits] [mlir] [mlir][Vector] Reject invalid inline yields (PR #206218)

[llvmlistbot at llvm.org]

https://github.com/mygitljf created https://github.com/llvm/llvm-project/pull/206218

I tightened Vector inlining so `vector.yield` is only considered inlineable in the vector region shape that owns its semantics. This keeps mixed-dialect function bodies from reaching the generic terminator hook path that Vector does not implement.
fixes #206083

>From 4064a658a86f66314b5b6dad417a13713dcea9ef Mon Sep 17 00:00:00 2001
From: mygitljf <2410316423 at qq.com>
Date: Sat, 27 Jun 2026 12:19:34 +0000
Subject: [PATCH] [mlir][Vector] Reject invalid inline yields

---
 mlir/lib/Dialect/Vector/IR/VectorOps.cpp |  5 ++---
 mlir/test/Dialect/LLVMIR/inlining.mlir   | 15 +++++++++++++++
 2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/mlir/lib/Dialect/Vector/IR/VectorOps.cpp b/mlir/lib/Dialect/Vector/IR/VectorOps.cpp
index 67c31730f4b65..443e41187efac 100644
--- a/mlir/lib/Dialect/Vector/IR/VectorOps.cpp
+++ b/mlir/lib/Dialect/Vector/IR/VectorOps.cpp
@@ -464,9 +464,8 @@ namespace {
 struct VectorInlinerInterface : public DialectInlinerInterface {
   using DialectInlinerInterface::DialectInlinerInterface;
 
-  /// All vector dialect ops can be inlined.
-  bool isLegalToInline(Operation *, Region *, bool, IRMapping &) const final {
-    return true;
+  bool isLegalToInline(Operation *op, Region *, bool, IRMapping &) const final {
+    return !isa<vector::YieldOp>(op) || isa<vector::MaskOp>(op->getParentOp());
   }
 };
 } // namespace
diff --git a/mlir/test/Dialect/LLVMIR/inlining.mlir b/mlir/test/Dialect/LLVMIR/inlining.mlir
index 85cae992f01de..a41f66a17be12 100644
--- a/mlir/test/Dialect/LLVMIR/inlining.mlir
+++ b/mlir/test/Dialect/LLVMIR/inlining.mlir
@@ -794,3 +794,18 @@ llvm.func @caller_cf_br_terminator(%arg0 : i64) -> i64 {
   %0 = llvm.call @callee_cf_br_terminator(%arg0) : (i64) -> i64
   llvm.return %0 : i64
 }
+
+// -----
+// Skip callees with non-LLVM function exits.
+
+llvm.func @callee_vector_yield_terminator(%arg0 : vector<8xf32>) {
+  %0 = math.atanh %arg0 : vector<8xf32>
+  vector.yield %0 : vector<8xf32>
+}
+
+// CHECK-LABEL: @caller_vector_yield_terminator
+llvm.func @caller_vector_yield_terminator(%arg0 : vector<8xf32>) {
+  // CHECK: llvm.call @callee_vector_yield_terminator
+  llvm.call @callee_vector_yield_terminator(%arg0) : (vector<8xf32>) -> ()
+  llvm.return
+}