[Mlir-commits] [mlir] [mlir][XeGPU][Transform] Add gather/scatter coalescing analysis. (PR #201684)

[Md Abdullah Shahneous Bari]

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@@ -927,6 +927,49 @@ def XeGPU_MemLayoutAttr : XeGPUAttr<"MemLayout", "mem_layout"> {
 
 }
 
+def XeGPU_CoalesceHintAttr : XeGPUAttr<"CoalesceHint", "coalesce_hint"> {
+  let summary = [{Optional request to coalesce a gather/scatter access.}];
+
+  let description = [{
+    `CoalesceHintAttr` is the optional `coalesce_hint` attribute of
+    `xegpu.load` / `xegpu.store`. It requests that the access group `factor`
+    contiguous elements per lane along the innermost (fastest-changing)
+    dimension of the offsets. `factor` must be a power of two `>= 2`, and the
+    innermost offsets dimension must be a multiple of it.
+
+    The hint has two sources:
+      - it can be set directly by the user (or a higher-level frontend that
+        already knows the access is contiguous-per-lane), in which case the
+        coalesce-gather-scatter analysis is not consulted for that op; or
+      - it is stamped by the analysis when it proves the access coalescible.
+
+    The hint is a *request*, not a commitment: a consumer turns `factor` into
+    a concrete `xegpu.layout` (deriving the `lane_layout` / `lane_data` split
+    from the op's offsets inner extent and the chip's subgroup size) and
+    clears the hint. A consumer that declines (for example, layout propagation
----------------
mshahneo wrote:

Done.
It's now `contiguous_chunk` (an `OptionalAttr<I64Attr>`, identical in shape to the existing `chunk_size`), carrying the inner-dim contiguity directly. 
**Naming note:** I went with contiguous_chunk rather than contiguity because the longer-term plan is to fold this into chunk_size once the separate chunk_size-removal lands — at which point this is a pure rename. The description no longer ties it to coalescing; it just states the property and notes consumers may use or ignore it.


https://github.com/llvm/llvm-project/pull/201684