[Mlir-commits] [mlir] [mlir][vector] add consistent stride verification to `masked load/store` and `gather/scatter` ops (PR #204842)
Andrzej WarzyĆski
llvmlistbot at llvm.org
Fri Jun 19 07:57:24 PDT 2026
================
@@ -1413,6 +1413,15 @@ func.func @maskedload_memref_mismatch(%base: memref<?xf32>, %mask: vector<16xi1>
// -----
+func.func @maskedload_negative_stride(%flip: memref<100x100xf32, strided<[-100, 1]>>, %mask: vector<8xi1>, %pass: vector<8xf32>) -> vector<8xf32> {
+ // expected-error @+2 {{'vector.maskedload' op memref strides must be non-negative}}
+ %c0 = arith.constant 0 : index
+ %0 = vector.maskedload %flip[%c0, %c0], %mask, %pass : memref<100x100xf32, strided<[-100, 1]>>, vector<8xi1>, vector<8xf32> into vector<8xf32>
+ return %0 : vector<8xf32>
+}
----------------
banach-space wrote:
[nits] Please use consistent variable names (`%flip` -> `%src`). Also, `%c0` could be an argument (you can rename as `%idx`).
https://github.com/llvm/llvm-project/pull/204842
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