[Mlir-commits] [mlir] [MLIR][XeGPU] Enable `isa<>` check for uarch (PR #204577)

[Jianhui Li]

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@@ -152,16 +153,49 @@ struct CacheInfo {
 };
 
 struct uArch {
+  enum class Kind {
+    // Xe2 family
+    Xe2Plus_First,
+    PVC = Xe2Plus_First,
+    BMG,
+    CRI,
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Jianhui-Li wrote:

Better to separate to Xe2 (PVC/BMG) and Xe3 (CRI) family to allow target-family specific check. 

https://github.com/llvm/llvm-project/pull/204577