[Mlir-commits] [llvm] [mlir] [SDAG][NVPTX] Enable custom legalization of v1 type for Intrinsic results and operands (PR #203237)

[Pradeep Kumar]

schwarzschild-radius wrote:

> Do I understand it correctly that the uniform lowering of v1 vector is the only goal here. I.e. there are no functional issues, just code clean-up?

Thanks for the review, @Artem-B! That's right uniform lowering of v1 vector type is the only goal of this PR

https://github.com/llvm/llvm-project/pull/203237