[Mlir-commits] [mlir] [MLIR][XeGPU] Enable peephole optimization for the CRI target (PR #201655)

[Jianhui Li]

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@@ -80,13 +80,17 @@ getMaybeLaneLayout(xegpu::TensorDescType tdescType) {
 /// tensor_desc to i32 type such that lane data becomes [1, 1]. This makes the
 /// later lowering easily use the load with transpose instruction.
 static bool canBeOptimizedForTranspose(ArrayRef<int64_t> laneLayout,
-                                       ArrayRef<int64_t> laneData) {
+                                       ArrayRef<int64_t> laneData,
+                                       int64_t elementBitWidth) {
   if (laneLayout.size() != 2 || laneData.size() != 2)
     return false;
   if (laneLayout[0] == 1 || laneLayout[1] != 1)
     return false;
   if (laneData[0] != 1 || laneData[1] == 1)
     return false;
+  // Add a tighter check to see if the bundle to transpose is 32bit.
+  if (elementBitWidth * laneData[1] != 32)
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Jianhui-Li wrote:

why this is necessary? 

https://github.com/llvm/llvm-project/pull/201655