[Mlir-commits] [mlir] [MLIR][XeGPU] Support plain 8-bit load_nd in XeVM lowering (PR #201645)

[Jianhui Li]

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@@ -431,10 +431,18 @@ class LoadStorePrefetchNdToXeVMPattern : public OpConversionPattern<OpType> {
           rewriter.eraseOp(op);
         } else {
           VectorType dstVecTy = cast<VectorType>(op.getValue().getType());
-          const bool vnni = op.getPacked().value_or(false);
+          bool vnni = op.getPacked().value_or(false);
           auto transposeValue = op.getTranspose();
           bool transpose =
               transposeValue.has_value() && transposeValue.value()[0] == 1;
+          // Handle special case of plain 8bit element load
+          // with no vnni, no transpose, no vblocks
+          // Turn on vnni since non vnni load is not valid.
+          // vnni and non vnni yields the same output so they can
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Jianhui-Li wrote:

I think that this statement is not correct. 
Refer to https://github.khronos.org/SPIRV-Registry/extensions/INTEL/SPV_INTEL_2d_block_io.html  Mapping Block Data to Invocations
Consider subgroup size = 16 and tile<8x32xi8>. 
For lane0: VNNI load returns 
[0, 0] [1, 0] [2, 0] [3, 0], [0, 16] [1, 16] [2, 16] [3, 16],  [4, 0] [5, 0] [6, 0] [7, 0], [4, 16] [5, 16] [6, 16] [7, 16]
non VNNI load returns:
[0, 0]  [0, 16],  [1, 0] [1, 16], [2, 0] [2, 16],  [3, 0] [3, 16] ...

For <8x16xi8>, it happens to be same but it is not highest-perf shape since it only runs at half of capacity. Does dpas support A as <8x16xi8>, I though it has be 8x32xi8? 

https://github.com/llvm/llvm-project/pull/201645