[Mlir-commits] [mlir] [mlir][SPIR-V] Add OpenCL erfc op (PR #201906)

[Arseniy Obolenskiy]

https://github.com/aobolensk updated https://github.com/llvm/llvm-project/pull/201906

>From 35ab601d6e5d188f76520078ee6725fb2d642f0f Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Fri, 5 Jun 2026 20:38:52 +0200
Subject: [PATCH 1/2] [mlir][SPIR-V] Add OpenCL erfc op

---
 .../mlir/Dialect/SPIRV/IR/SPIRVCLOps.td       | 23 +++++++++++++++++++
 mlir/test/Target/SPIRV/ocl-ops.mlir           |  2 ++
 2 files changed, 25 insertions(+)

diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCLOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCLOps.td
index 6ecf85adaaf6d..539958f1cb085 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCLOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVCLOps.td
@@ -340,6 +340,29 @@ def SPIRV_CLCoshOp : SPIRV_CLUnaryArithmeticOp<"cosh", 15, SPIRV_Float > {
 
 // -----
 
+def SPIRV_CLErfcOp : SPIRV_CLUnaryArithmeticOp<"erfc", 17, SPIRV_Float> {
+  let summary = [{
+    Complementary error function of x.
+  }];
+
+  let description = [{
+    Result Type and x must be floating-point or vector(2,3,4,8,16) of
+    floating-point values.
+
+    All of the operands, including the Result Type operand, must be of the
+    same type.
+
+    #### Example:
+
+    ```mlir
+    %2 = spirv.CL.erfc %0 : f32
+    %3 = spirv.CL.erfc %1 : vector<3xf16>
+    ```
+  }];
+}
+
+// -----
+
 def SPIRV_CLErfOp : SPIRV_CLUnaryArithmeticOp<"erf", 18, SPIRV_Float> {
   let summary = [{
     Error function of x encountered in integrating the normal distribution.
diff --git a/mlir/test/Target/SPIRV/ocl-ops.mlir b/mlir/test/Target/SPIRV/ocl-ops.mlir
index 227ec5093deaf..b091c972c966c 100644
--- a/mlir/test/Target/SPIRV/ocl-ops.mlir
+++ b/mlir/test/Target/SPIRV/ocl-ops.mlir
@@ -37,6 +37,8 @@ spirv.module Physical64 OpenCL requires #spirv.vce<v1.0, [Kernel, Addresses, Vec
     %9 = spirv.CL.rsqrt %arg0 : f32
     // CHECK: {{%.*}} = spirv.CL.erf {{%.*}} : f32
     %10 = spirv.CL.erf %arg0 : f32
+    // CHECK: {{%.*}} = spirv.CL.erfc {{%.*}} : f32
+    %erfc = spirv.CL.erfc %arg0 : f32
     // CHECK: {{%.*}} = spirv.CL.trunc {{%.*}} : f32
     %11 = spirv.CL.trunc %arg0 : f32
     spirv.Return

>From e16a08f954f179e07771737f1a08c6f643c4902e Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Fri, 5 Jun 2026 20:46:44 +0200
Subject: [PATCH 2/2] Add missing dialect tests

---
 mlir/test/Dialect/SPIRV/IR/ocl-ops.mlir | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/mlir/test/Dialect/SPIRV/IR/ocl-ops.mlir b/mlir/test/Dialect/SPIRV/IR/ocl-ops.mlir
index f4612d9c3bf4f..68d5d941e4fef 100644
--- a/mlir/test/Dialect/SPIRV/IR/ocl-ops.mlir
+++ b/mlir/test/Dialect/SPIRV/IR/ocl-ops.mlir
@@ -632,6 +632,22 @@ func.func @cosh(%arg0 : vector<4xf16>) -> () {
 
 // -----
 
+func.func @erfc(%arg0 : f32) -> () {
+  // CHECK: spirv.CL.erfc {{%.*}} : f32
+  %2 = spirv.CL.erfc %arg0 : f32
+  return
+}
+
+// -----
+
+func.func @erfc(%arg0 : vector<4xf16>) -> () {
+  // CHECK: spirv.CL.erfc {{%.*}} : vector<4xf16>
+  %2 = spirv.CL.erfc %arg0 : vector<4xf16>
+  return
+}
+
+// -----
+
 func.func @asin(%arg0 : f32) -> () {
   // CHECK: spirv.CL.asin {{%.*}} : f32
   %2 = spirv.CL.asin %arg0 : f32