[Mlir-commits] [mlir] [MLIR][NVGPU] Add convert.fpext and convert.fptrunc Ops (PR #199700)

[Guray Ozen]

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@@ -671,4 +671,80 @@ def NVGPU_RcpOp : NVGPU_Op<"rcp", [Pure,
   let hasVerifier = 1;
 }
 
+//===----------------------------------------------------------------------===//
+// NVGPU Conversion Ops
+//===----------------------------------------------------------------------===//
+
+def Int8OrFloatLike : TypeConstraint<
+    Or<[FloatLike.predicate,
+        I8.predicate,
+        ValueSemanticsContainerOf<[I8]>.predicate]>,
+    "scalar, vector, or tensor of i8 or floats">;
+def AnyI32Like : TypeOrValueSemanticsContainer<I32, "scalar i32 or vector of i32">;
+
+def NVGPU_FPTruncOp : NVGPU_Op<"convert.fptrunc",
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grypp wrote:

I agree that today src/dst are not the same. But as HW evolves, I think we will complete the matrix.

> 2)
> Some input operands are required for one but not the other.
> For example, random_bits is a possible input for trunc but not for ext.
> 3) 
> The set of required attrs differs between the two.
> For example, ext does not need rounding-mode attr.

On verifier, don't we always know truncation or extension? With this in mind, we can allow/disallow attributes. 

NVGPU is kind of a frontend dialect now, so we will immediately lower to NVVM dialect/intrinsics where is optimizable. 

To reference in TileIR, we have [cuda_tile.ftof](https://docs.nvidia.com/cuda/tile-ir/latest/sections/operations.html#op-cuda-tile-ftof) converts between different floating-point types.

https://github.com/llvm/llvm-project/pull/199700